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LVDS receivers: signaling rates

Other Parts Discussed in Thread: SN75LVDS386, SN65LVDS389, SN65LVDS387

In the search for wide LVDS receivers for clock frequencies up to 312 MHz, I have come to a surprising fact that has confused me. Parameric table uses the concept 'signaling rate', which is somehow related to clock rate.

For example, the SN75LVDS386 is said to be designed for signaling rates up to 250 MHz (Table 1) but later (page 2 of datasheet), it states 'When used with its companion, 8- or 16-channel driver, the SN65LVDS389 or SN65LVDS387, over 300 million data transfers per second in single-edge clocked systems are possible with little power''. I understand this is an example of conservative specification, which in practise turns out to be good enough for higher data rates.

In my humble oppinion, the parameters that have influence in clock rate are:

  • Propagation delay
  • Rise and fall time
  • Skew
  • Ground bounce due to simultaneous switching outputs (SSO)

For a system like mine, it seems I should not use 75LVDS386 receiver because it has been designed for just 250 MHz signaling rate. Instead of that I could use the Quad 65LVDS349 which is specified for a single channel signaling rat of 560 Mbps. However propagation delay of the later turns out to be higher (4 ns vs 2.6 ns, to compare typical values), and so is rise/fall time (1.2/1 ns vs 0.8 ns). This makes me thing if LVDS386 is underspecified and LVDS349 overspecified.

In my application there is also a intrinsig advantage of 75LVDS386: being a 16 bit device, skew is limited to a single chip.

Figures 15 and 16 in LVDS386 suggest me I could use it safely in my application.

Summarizing: From every aspect, it seems I should use LVDS386, but the signaling rate specification for it stops me. Could you give more slight into this 'signaling rate' specification?

Best regards

Luis Miguel