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TIDA-00175 Interface to a 5V BiSS Position Encoder Reference Design

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Hello

I have a question about the Document "TIDU410". In chapter 6.1.4 (page 31) there is described that a BER of 10^-7 can be seen as error-free. On what is the maximum BER in the transmission based on? Is there a standard or rule?

Greetings from Germany

Viktor M.

  • Greetings Viktor,

    I am currently tracking down the producer of this TI design so that they may offer an explanation for their testing. Someone will follow up with you shortly.



    Regards,

    Michael Peffers

    Industrial Interface Applications

    Analog Wire: Get Connected

  • In reply to Michael Peffers:

    Hello Viktor,

    thank you for your interst on our design and your question.

    To your question: How did we come to a 10-7 BER.

    For the test on maximum clock frequenc over cable length we increased the BiSS MA-clock frequency until
    a bit error occurred on the received data frame (SL).

    Only if no bit error occurred, the test passed and only then we claimed an "error free" data rate, with
    BER <10-7 due to a limited 60 s test time. This scenario should simulate a typical servo drive’s inner
    current control loop (FOC) running at, for example, 8 kHz, and requesting a new digital-angle position
    through BiSS interface at this rate.

    Why can we only claim BER < 10-7 although no bit error: We transmitted 64-bits @8Khz over 60sec. The total number of bits
    transmitted during this period was 3.072 x 10+7. Hence no bit error in 3 x 10+7 bits.

    Due to the limited amount of bits transmitted we only could claim we are at least better than 10-7 (actually better than 0.3 x 10-7)
    We coculdn't claim we are better 10-8 or higher simply because we didn't conduct the the test long enough.
     
    Does this answer your question?

    Regards,
    Martin Staebler

  • In reply to Martin Staebler:

    Hi Martin

    thank you for your answer. Therefore there isn't a rule for this test. What will happen if a biterror occurs? Will the controller stop instantly, or is there a number of biterrors allowed?

    Regards,

    Viktor M.

  • In reply to Viktor Michel:

    Hi Viktor,

    this is a question on how the BiSS-C Master is implemented on the processor connected to our design. The TIDA-00175 won't be affected by a bit error, it will just relay it to the digital 3.3V interface which connects to a processor with BiSS-C Master. 

    In a drive application the BiSS-C master would periodically request the position from the BiSS encoder and the encoder would send the data packet according to the BiSS-C protocol. There's a CRC error check implemented. If the BiSS-C master detects a CRC error, it will be a user specification how to handle this.

    It may send another request for position (if still possible in the current control cycle), it may use an estimated position instead, or it even may shutdown the drive (safe torque off). All this is specified by the user.

    TI has a design which shows a BiSS-C Master on Sitara ARM processors:http://www.ti.com/tool/TIDEP0022

    Are you planning to implement a BiSS-C master or slave?

    Thanks.

    Regards,

    Martin

  • In reply to Martin Staebler:

    Hi Martin

    No, actually i'm not planning to implement a BiSS-C Interaface. I just want to know differences between different types of interfaces. Anyway, thank you for your reply. My question about  the BER of 10^-7 is answered. Do you know where i can inform me about "current control cycle"? How is it defined? 

    Best Regards, 

    Viktor

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