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We are considering using the DS90UB927Q-Q1 and the DS90UB928Q-Q1 in an upcoming design. Looking for app notes, layout guidelines, as well as ESD protection recommendations for these parts.
Have this infromation with me.
Technical Documents Folder: http://www.ti.com/product/DS90UB927Q-Q1/technicaldocuments
Application report: http://www.ti.com/lit/an/snla221/snla221.pdf
User Guide: http://www.ti.com/lit/ug/snlu125/snlu125.pdf
Technical Documents Folder: http://www.ti.com/product/DS90UB928Q-Q1/technicaldocuments
User Guide: I could not find a layout but am checking with the product line.
Product Folder: http://www.ti.com/product/tpd4e001-q1
Product Folder: http://www.ti.com/product/TPD4E05U06-Q1/datasheet
The question about ESD is a bit more specific. What I wanted to ask is this: both the serializer and deserializer have built-in ESD protection listed in the datasheet. Out FPDLink outputs and inputs are interfaced with an RJ45 connector on both sides of the link. We have a requirement for discharge into each of the pins (belwo in red). In light of these requirements I am wondering if TI recommends additional ESD protection or if you feel the part will be sufficient. Given the higher resistance specified I suppose so, but I am checking for completeness.
Also looking through the application note schematics I noticed that there is common mode choke on the output of the FPDLink. The particular choke used has about 2.5dB of insertion loss at 4.5Ghz which is pretty much the third harmonic of the fundamental when the part is operating at ~3Gbps worst case. (Generally we assume that the band occupied by the forward channel on FPD-III will be from ~1/20 the bit rate to ~1/2 of the bit rate. We design for the worst case. This means NRZI encoding I assume. Is this correct and if not where can we find out more about the specific modulation/ coding scheme to ensure that we are meeting link requirements.) If used on both sides of the link, the use of a choke will result in about a 5dB reduction in SNR on the third harmonic and some distortion of the waveform; the extent of distortion depending on the intrinsic filtering of the output. Assuming that all other factors remain constant this is pretty large. We have a couple of questions relating to this.
Is the choke required for EMC/RFI performance?
Do we care about 3rd harmonic distortion or is the use of the choke a pretty small effect? ( I suspect so but would like confirmation) Specifically, does TI have information regarding how sensitive the link is to third harmonic distortion or can we be provided with a spectral mask for typical random, worst case transmission?
This last question is important when considering ESD protection requirements.
SAE ESD requirements
SAE J14551 Section 184.108.40.206.3 and SAEJ1113-13
ESD Classification for handling: System status = unpowered, Discharge Network = 150 pfd & 150 W, Discharge to each individual pin & surface.
No damage or degradation
Must withstand 3 applications of +/- 15 KV Each pin must be tested 3 times with each polarity.
TI ESD specs from Datasheet:
ESD Rating (IEC, powered-up only), RD = 330Ω, CS = 150pF
Air Discharge (RIN±, CMLOUTP/CMLOUTN) ≥±15 kV
Contact Discharge (RIN±, CMLOUTP/CMLOUTN) ≥±8 kV
ESD Rating (ISO10605), RD = 330Ω, CS = 150pF
Air Discharge RIN±, CMLOUTP/CMLOUTN) ≥±15 kV
Contact Discharge RIN±, CMLOUTP/CMLOUTN) ≥±8 kV
ESD Rating (ISO10605), RD = 2kΩ, CS = 150pF or 330pF
Contact Discharge(RIN±, CMLOUTP/CMLOUTN) ≥±8 kV
ESD Rating (HBM) ≥±8 kV
ESD Rating (CDM) ≥±1.25 kV
ESD Rating (MM) ≥±250 V
Thanks for your help!
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