DS90UB913Q/914Q evalution kit

Thanks Sean for your prompt response, I am studying these documents, If there any technical query I will post it.As of now, we, development team only have serializer board in our product, for de-serializer we order evaluation board from TI which we were told out of stock.We are trying to get it ASAP. But if we failed to have it, may I know is there any simulator available for LVDS so that we can start and test our communication and expedite our development.

Please share any document if you have for these simulator.

Thanks and Regards

Rajan Joshi

Hello Rajan,

In the interim, you can use the IBIS models to simulate your design:

http://www.ti.com/product/DS90UB913Q-Q1/toolssoftware

http://www.ti.com/product/DS90UB914Q-Q1/toolssoftware

-Sean

Sean, Thanks for your prompt response again.

I downloaded this model for 913/4 devices but I dont find any information about how to use them? Do they required SPICE model software(as I searched on internet). I dont know much about SPICE and its licensing as I use company's laptop . Can you guide me to how to use IBIS model on PC to use 913 standalone?

Thanks again,

Warms Regards

Rajan Joshi

Hi Technical Support Team,

I am trying to connect Serializer and Deserilizer DS90UB913Q/914Q evalution kit together. I get below Observation:

  1) Lock LED is not glowing and continuosly coming Low on DES board.

2) 0x0c register after reading shows value 0x04 which means 72MHz PLL detect is ok, cable is open, there is no link between SERDES?

3) 0x06 DES ID is not getting configured.

I have queries here.

So here I want SER to work as slave proxy and DES as master proxy, so may I know what register I actually need to configure to establish link between SERDES?

Can SER DES link estblish stand along without I2C communication?

Link between SER and DES should be establised irrespective of PCLK and external oscillator, please confirm?

As you see in point 2 above link is not getting established as told by status register 0x0C

Can you guide us on above points?

Hello Rajan,

The SER DES forward link can be established without back channel link (i.e. I2C communication) . The back channel link sends data from DES to SER which is control data - for example, I2C data or GPIO data. I2C data and GPIO data can also be sent in the forward direction in addition to primary video data.

Have there been any modifications to the 913Q/914Q evaluation boards? Just these stand-alone boards should LOCK when connected together unless 1) the cable is a very high loss (i.e. unshielded) cable or 2) the cable is very long and cable loss is high enough to cause loss of LOCK 3) there have been modifications. Also, do you connect an imager sensor to the 913Q side? Please connect 913Q and 914Q together as stand alone and see if there is LOCK. The PCLK output on the 914Q board should be ~ 50 MHz since this is the internal oscillator frequency that is generated and sent as PCLK from 913Q board.

What cable is being used and what is the length? Are you running in External oscillator mode or Direct PCLK mode? is your PCLK = 72 MHZ and are you running in 10-bit or 12-bit high frequency mode?

0x0C register on 913Q gives a lot of details about the system. Typically you want to see bit 0 = 1 since this is the BACK CHANNEL link detect, not forward channel link detect. If this bit = 0 which you mention, then yes your back-channel data is not getting from DES to SER. Please make sure that on 914Q the register 0x01[2] = 1. This is the back channel enable bit and will be enabled by default but can be disabled through register write over I2C. This answers question 3) for why DES ID on Serializer is not getting configured.

Once LOCK is established on the evaluation boards, the back channel LINK should be established as well as long as 0x01[2] = 1.

Hey Thanks a lot.

It was problem in cable as you said and we sorted out by connecting it by FRC cable.

Now EVM is working.

Thanks a lot for your prompt help.

Now we are studying registers of LVDS and below things are on our agenda:

913:

Register 0x0F[1]: I2C bus timer Speed up: what happen when watchdog expires?

Register 0x0A and 0x0B: On which field CRC applied? How can we crosscheck CRC for error checking?

914:

What is parity errors and threshold Register[0x18]?

Register 0x21:I2C control 1: What is forward channel sequence error?

Understanding timing diagram for SDA output delay if any?

What is CRC force error Reg[0x42]?

What is AEQ test mode[0x4D]?

 I will finish this assignment and will come back to you if any query.Meanwhile It will be a great help if you have any ready reference/answers for above which will save lots of our time in understanding SERDES.

Thanks again for your previous help on link detection issue.

Best Regards

Rajan