Hello,
I have a DS92LV2411 and a DS92LV2412 on one PCB that are functioning properly in BIST mode and with static signals at the input of the 2411.
When applying a signal of about 10kHz the 2412 loses the PLL-LOCK state.
The clock frequency of the 2411 is 5MHz, all strap pins are 0, startup delay of VDD and PDB is 200ms for correct configuration detection.
All supply voltages are blocked, the measured ripple is round about 5mV.
Thanks
Mario
ello,
the link between the devices is a fiber-optic (differential - single ended transceiver in between).
Now link with a twisted pair 100nF in series, length ~20cm, no change in the behaviour.
The 5 MHz crystal is always connected, also when BIST is enabled.
When applying a frequency from 100Hz to 200kHz the DS92LV2412 locks for some time and looses after some ms the link.
PASS and LOCK are flickering.
The VDD ramps in about 1ms from 0V to 1.8V the 3.3 VDDIO needs 2.8ms but the difference between PDB and VDD is 200ms,
therefore according NOTE 1) it should be ok.
This is the signl measured at the input of the 2412 with 100kHz input signal at Din2.
I did some tests with OSC pin of the 2411 connected to a waveform generator to adjust different clocks.
After rising the clock over 6MHz the link started to work :-)
But I don´t know why, is there something like aliasing or undersampling at 5MHz clock and 100kHz data at input?
Regards
Mario
