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How to use DS100DF410 Prbs generator

Other Parts Discussed in Thread: DS110DF111, DS100DF410

We are using internal PRBS generator for testing. But oscilloscope show could not recovery clock.

We had configed with the sequen below:

p i2c_write_byte(0, 0x70, 1, 1)              //I2C switch
p i2c_write_byte(0, 0x18, 0xff, 0x7)      //select chanel
p i2c_write_byte(0, 0x18, 0x00, 0x04)  //reset retimer
p i2c_write_byte(0, 0x18, 0x2d, 0x89)  //set post-emphasis
p i2c_write_byte(0, 0x18, 0x15, 0x52)  //set amplitude
p i2c_write_byte(0, 0x18, 0x14, 0x80) 
p i2c_write_byte(0, 0x18, 0x09, 0xec)
p i2c_write_byte(0, 0x18, 0x1b, 0x00)
p i2c_write_byte(0, 0x18, 0x08, 0x07)
p i2c_write_byte(0, 0x18, 0x18, 0x00)
p i2c_write_byte(0, 0x18, 0x1f, 0x52)
p i2c_write_byte(0, 0x18, 0x1e, 0x99)
//PRBS_31
p i2c_write_byte(0, 0x18, 0x30, 0x0a)
//PRBS_9
p i2c_write_byte(0, 0x18, 0x30, 0x08)
p i2c_write_byte(0, 0x18, 0x0d, 0x20)

The datasheet has some incorrect discription, so i Refer to the configuration mentioned in the link below

e2e.ti.com/.../277277

what can i do next?

  • Hi,

    Is the output muted or is the output active (simple trigger on edge)?

    Using the free running VCO will result in a wandering and non-exact output datarate.  It is possible the actual datarate is not what is expected.

    I have tested the sequence in the DS110DF111 datasheet many times - note that the order and bits which are written is very specific.

    Regards,

    Lee

  • Hi,

    thank you for your reply.

    1.The output is active,we used the oscilloscope PRBS31 test program.Without configuration it can be tested, after configured then remind cannot recovery the clock.If use PRBS9 test program,it remind incorrect pattern detected.

    2.I will try again with the datasheet of DS110DF111.

    Regards,

    He

  • Hi,

    I had tried the sequence in the DS110DF111 datasheet, it also reminded 'is unable to recover a clock on f1:Ch1 - Ch3,Decrease loop bandwidth and check thresholds'.

    After I modify the value of Register 0x08, and I chane it from 0x06 to 0x08, then it becomes can be tested. But I still have a question, It can be tesetd at the range of the value of Register 0x08 from 0x08 to 0x15, how shuld I choose the correct value? Different value will Impact test results.

    Tks!

  • I would choose a value in the middle of the range which produces good test results, about 0x0F in your case.  I cannot think of a test which would help you choose the optimal value.

    Regards,

    Lee

  • Thank you for your help! We had finished the eye onpening test.
    I have another question, if I can swap chanel between two chanels in DS100DF410, for example chanel 0 RX connect to chanel 1 TX and chanel 1 Rx connect to chanel 0 TX.
  • Hi Hui,

    The DS100DF410 does not have internal paths to swap or fanout channels.  There is a similar two channel device, DS110DF111 which can swap or fanout channels.

    Regards,

    Lee 

  • Hi Lee,

    I'm sorry for another question, My system diagram is Cavium CPU <--> DS100DF410 <--> SFP+.

    How should I confirm if I should use the DEF adapter between CPU and DS100DF410.The layout length of serdes is 1600mil to 2500 mil for different port, every port with one pair vias.

  • Hi Hui,

    I would enable the DFE.  With these relatively short transmission lines which include vias there is a real possibility for reflections to impact the jitter.  You can look at the optimized DFE values and HEO/VEO values in the registers to see if DFE is having a positive impact on the eye opening.  If it is not needed, you can disable the feature and save on some power.

    Regards,

    Lee