Hi Team,
DS90UB954-Q1 has two differential clock outputs (CSI_CLK0P/N and CSI_CLK1P/N).
I believe CSI_CLK0P/N should be connected to processor SOC when CSI_LANE_COUNT=00 (4 lanes) regardless of input is RX0+/- or RX1+/-.
Is my understanding correct?
Best Regards,
Yaita / Japan disty