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DS90UB954-Q1: CSI_CLK0P/N and CSI_CLK1P/N

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Part Number: DS90UB954-Q1

Hi Team,

DS90UB954-Q1 has two differential clock outputs (CSI_CLK0P/N and CSI_CLK1P/N).
I believe CSI_CLK0P/N should be connected to processor SOC when CSI_LANE_COUNT=00 (4 lanes) regardless of input is RX0+/- or RX1+/-.
Is my understanding correct?

Best Regards,
Yaita / Japan disty

  • Hello,

    When you are using 4 lanes, the CSI_CLK0P/N will contain the clock information. CSI_CLK1P/N is used when there are two sets each consisting of two lanes. CSI_CLK1P/N is the clock for the second set of lanes.

    Please see the Pin Description for the CSI pins on page 4 of the datasheet. Also see Figures 50 to 53 in the datasheet. Figure 50, 51 and 53 will use CSI_CLK0P/N, Figure 52 uses both CSI_CLK0P/N and CSI_CLK1P/N.

    Mike

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