hi，
I am using the Xilinx Display port(RX) IP v7.0 in my design with Xilinx K7。DP159 as the retimer。When in TP1 Interrupt Handler ， the GTX can not locked the recovered clk。Measure the frequency of the AUX_SRCp/n pin with an oscilloscope，Frequencies sometimes in the 300MHZ, sometimes about 50MHZ 。
The following is my initialization Dp159 register configuration
thanks ！！！
//dp159 config
//initial
//Page 0
instruction_set[0] = {WRITE, 8'hFF, 8'h00} ; //Select Page 0
instruction_set[1] = {WRITE, 8'h09, 8'h36} ; //Enable X-Mode
instruction_set[2] = {WRITE, 8'h0A, 8'h7B} ; //Disable HPD_SNK pass thru to HPD_SRC.
instruction_set[3] = {WRITE, 8'h0D, 8'h80} ; //Enable clock on AUX. Select 1/20 mode.
instruction_set[4] = {WRITE, 8'h0C, 8'h6D} ; //Set TX Swing to Max
instruction_set[5] = {WRITE, 8'h10, 8'h00} ; //Turn off pattern verifier
instruction_set[6] = {WRITE, 8'h16, 8'hF1} ; //Disable char-alignment on all lanes.
instruction_set[7] = {WRITE, 8'hFF, 8'h01} ; // Select Page 1
//CONFIGURE PLL BLOCK
instruction_set[8] = {WRITE, 8'h00, 8'h02} ; //Enable Bandgap.
instruction_set[9] = {WRITE, 8'h04, 8'h80} ; //PLL_FBDIV[7:0]
instruction_set[10] = {WRITE, 8'h05, 8'h00} ; //PLL_FBDIV[10:8]
instruction_set[11] = {WRITE, 8'h08, 8'h00} ;
instruction_set[12] = {WRITE, 8'h0D, 8'h02} ; //Select LN0 for clock.
instruction_set[13] = {WRITE, 8'h0E, 8'h03} ; //CDR_CONFIG[4:0]. FIXED, LN0.
instruction_set[14] = {WRITE, 8'h01, 8'h01} ; //CP_EN is PLL mode
instruction_set[15] = {WRITE, 8'h02, 8'h3F} ; //CP_CURRENT is high.
instruction_set[16] = {WRITE, 8'h0B, 8'h33} ; //Loop Filter to 8K.
instruction_set[17] = {WRITE, 8'hA1, 8'h02} ; //Allows for Override of PLL settings.
instruction_set[18] = {WRITE, 8'hA4, 8'h02} ; //Allows for Override of PLL settings.
//CONFIGURE TX BLOCK
instruction_set[19] = {WRITE, 8'h10, 8'hF0} ; //ENTX for all four lanes (disable)
instruction_set[20] = {WRITE, 8'h11, 8'h30} ; //TX_RATE is Full Rate, TX_TERM = 75 to 150 , TX_INVPAIR = None
instruction_set[21] = {WRITE, 8'h14, 8'h00} ; //HDMI_TWPST1 is 0dB pre-emphasis
instruction_set[22] = {WRITE, 8'h12, 8'h03} ; //SLEW_CTRL is Normal, SWING is 600mV.
instruction_set[23] = {WRITE, 8'h13, 8'hFF} ; //FIR_UPD. Load TX settings
instruction_set[24] = {WRITE, 8'h13, 8'h00} ;
//CONFIGURE RX BLOCK
instruction_set[25] = {WRITE, 8'h30, 8'hE0} ; //Disable Receivers except lane 0
instruction_set[26] = {WRITE, 8'h32, 8'h00} ; //PD_RXINT
instruction_set[27] = {WRITE, 8'h31, 8'h00} ; //RX_RATE is Full
instruction_set[28] = {WRITE, 8'h4D, 8'h08} ; //EQFTC = 0 and EQLEV = 8
instruction_set[29] = {WRITE, 8'h4C, 8'h01} ; //Enable Fixed EQ
instruction_set[30] = {WRITE, 8'h34, 8'h01} ; //Enable Offset correction
instruction_set[31] = {WRITE, 8'h32, 8'hF0} ; //Load RX settings.
instruction_set[32] = {WRITE, 8'h32, 8'h00} ; //PD_RXINT
instruction_set[33] = {WRITE, 8'h33, 8'hF0} ; //Load EQ settings.
instruction_set[34] = {WRITE, 8'hFF, 8'h00} ; //Select Page 0
instruction_set[35] = {WRITE, 8'h0A, 8'h3B} ; //Enable HPD_SNK pass thru to HPD_SRC. Retimer
instruction_set[36] = {WRITE, 8'hFF, 8'h01} ; //Select Page 1
// TP1 Interrupt Handler
instruction_set[0] = {WRITE, 8'h10, 8'hF0} ; //Disable TX lanes
instruction_set[1] = {WRITE, 8'h00, 8'h02} ; //Disable PLL and clear A_LOCK_OVR
instruction_set[2] = {WRITE, 8'h01, 8'h01} ; //CP_EN = PLL (reference) mode
instruction_set[3] = {WRITE, 8'h0B, 8'h33} ; //Set PLL control
instruction_set[4] = {WRITE, 8'h02, 8'h3f} ; //Set CP_CURRENT
instruction_set[5] = {WRITE, 8'h30, 8'h0f};//Set RX Lane count
instruction_set[6] = {WRITE, 8'h00, 8'h03} ; //Enable Bandgap, Enable PLL, clear A_LOCK_OVR
instruction_set[7] = {WRITE, 8'h4C, 8'h01} ; //Enable fixed EQ
instruction_set[8] = {WRITE, 8'h4D, 8'h08} ;
instruction_set[9] = {WRITE, 8'h10, 8'h0f};//Enable TX lanes
instruction_set[10] = {WRITE, 8'h00, 8'h23} ; //Enable Bandgap, Enable PLL, set A_LOCK_OVR
The read value of reg 00 is 0xe3 .CLK is locked. But the DP159 output clock is wrong. Frequencies sometimes in the 300MHZ, sometimes about 50MHZ 。
