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SN65HVD11: about SN65HVD11D A/B port shorted current

Part Number: SN65HVD11

I'm using the HVD11 to drive 100ft of wire and associated emi filter capacitance to ground (7Mbps Manchester encoded format).  I want to make sure that output waveform does not become too rounded-off due to effects of part's output current limit.  Can you tell me if the IOS term "short-circuit output current" of +/-250mA will act as an instantaneous current limit?  Need to understand effects this may have on differential rise and fall times when driving a capacitive load.

  • Jeter,

    The IOS is more like a DC spec, when A/B pin is shorted to a supply. In your application, do you have any termination resistors on the bus? If you do, you can use the driver's rise time (around 20ns with 50Ohm and 50pF) to estimate the impact. The instantaneous current is about C(dV/dt). Unless the capacitor is huge, it might not be a concern.

    Regards,

    Hao

  • Thanks for your reply.  In my application we are driving 100ft of cable and some emi filter capacitance.  I have created a model for Transmitter with loading (capacitive and resistive) and rise/fall times in Pspice.  With these simulations I am see Driver instantaneous output currents reaching ~200mApk and I wanted to make sure the current limit wouldn't kick in causing additional reduction in rise/fall times of differential waveform.  In general with these parts is there anything within the part that would cause additional slew rate limiting like the current limit?

  • Jeter,
    I don't think ~200mA is regulated by the current limit circuit. There are no other circuitries to limit the slew rate either. Please let me know if you have more questions.
    Regards,
    Hao
  • Hao,

    The 200mA is what the Driver sources into the load for rise/fall times I have modeled.  All I'm saying is the instantaneous current the Driver may source/sink into the load can be quite high given the specified rise/fall times from the datasheet and the capacitive load that the part is required to drive in my application.  In this scenario I have no other current limiting in my Pspice model.  I want to make sure I understood the +/-250mA current limit specified in the datasheet and if it might perhaps act as an instantaneous current limit for higher capacitive loads.

    Thanks,

  • Jeter,

    You can consider the load capacitor C is charged/discharged by a small resistor R. If the driver has stronger driving capability, the value of the R would be smaller. If there are no parastics, the maximum current can flow through the R is the same as the current limiting. But in reality parastics also create current path. Therefore you might see the instantaneous current higher than IOS spec. I hope it makes sense to you. Please let me know if you have more questions.

    Regards,

    Hao

  • Hao,

    Not sure I completely understood your point.  Instantaneous current higher than IOS is ok for my application.  In fact this is desired to ensure no slew rate limiting when driving a capacitve load (long set of wires).  I just wanted to make sure I understood the Drivers capability so I had it modeled properly.

    Regards, 

  • Jeter,

    I draw a picture for your reference. The red line shows an extra current path during the fast transition due to the parasitic on IC. If the signal settles, the current limit dominates. Please let me know if you have more questions.

    Regards,

    Hao