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DS90UR910-Q1: DS90UR910-Q1 additional settings needed to Work in backward compatible GEN2 with Ser DS99R421Q 18-bit .

Anoop Sany
Prodigy 30 points
Part Number: DS90UR910-Q1

We are using Des DS90UR910-Q1  with Ser  DS99R421Q . What all are the additional settings required to be configured other than CONFIG[0:1] registers or gpio control . 

In our test set up we have configuired I2C reg 0x01 to work in GEN 2 mode . Now lock pin is showing high but no data is received through FPD link even though clock is received . Is there any special setup or configuration to be done to work DES DS90UR910-Q1 to work in GEN 2 mode with Ser DS99R421Q.

Thanks and regards,

Anoop

  • 0
    TI__Expert 7935 points
    Hello-

    -What is driving DS99R421Q?
    -Are you sending any data to the serializer?
    -Do you see high-speed data coming out of the DS99R421Q?

    Regards,
    Davor
  • 0 in reply to Davor Glisic
    Prodigy 30 points

    Hi Davor,

    -What is driving DS99R421Q?
    DS99R421Q is driven by IMX6D soc through 3 data + 1 clk LVDS. pixcel clock is 9.5 MHz
    -Are you sending any data to the serializer?
    -Do you see high-speed data coming out of the DS99R421Q?
    Yes data is being send through serializer and able to verified through a compatible head up display(Not sure about the HUD speciifcations)

    Moreover we are using QNX 7.0 RTOS . NXP iMX6D MIPI-CSI2 driver is provided by QNX itself. This driver is verified by PATGEN at desrializer ( DS90UR910-Q1).

    Is there anything special to be done to operate Der - DS90UR910-Q1 to support GEN2 , DS99R421Q 18-bit mode .

    Thanks and Regards,

    Anoop 

  • 0 in reply to Anoop Sany
    TI__Expert 4210 points

    Standard VESA video timing is required for the 910 to output.  PASS not at HIGH state indicates incorrect timing.

  • 0 in reply to Darryl Jeong
    Prodigy 30 points
    >>PASS not at HIGH state indicates incorrect timing.

    Pass is always high when there is a connection between Deserializer to serializer . PASS pin remains high even if no data is transmitted through FPD link . But PASS pin goes to LOW when the DES to SER FPD link channel is disconnected .

    >>Standard VESA video timing is required for the 910 to output.
    what are the parameters/registers to be set specifically .
  • 0 in reply to Anoop Sany
    TI__Expert 4210 points
    You need Vsynch, DE and PCLK.
    Guaranteed PCLK minimum for the 910 is 10MHz.