This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MAX3232E-Q1: Waveforms

Part Number: MAX3232E-Q1

[ MAX3232E-Q1 ] Waveforms

Hi,

My customer has been evaluating MAX3232E-Q1 on their board.
Can you help to review their waveforms as below?


<Q1: Voltage Bump on each High and Low>:



As you can see, the high and low level are dropped a bit while maintaining its level.
If it's measure without any load condition (open), no voltage drop can be seen.
Is this expected?


<Q2: Jitter>:



The jitter is somewhere around 90nS.
Is this what we expect?
Are there any jitter requirements on the industrial standard?

Thanks,
Ken

  • Hello,

    Yes, this is expected behavior. The device uses a charge pump to generate higher-voltage positive and negative reference voltages (V+ and V-) based on the VCC voltage provided. These reference voltages are used to drive the RS-232 outputs, so the high-state RS-232 output will match V+ and the low-state output will match V-. Each of these rails is expected to have some ripple, though, due to the switching nature of a charge pump. The frequency of this ripple will increase as the load on on the supply increases. Connecting a driver output to a receiver (such as a PC or the RIN input of a transceiver) will increase the loading, since RS-232 receiver inputs are specified to have a nominal input resistance of 5 kOhm.

    You can read more details about RS-232 charge pumps and see some example waveforms in this blog post:

    e2e.ti.com/.../how-the-rs-232-transceiver-s-regulated-charge-pump-circuitry-works

    Regarding the ripple, this looks typical to me as well. Jitter is not formally part of the RS-232 interface standard, but the maximum allowable level would be limited at a system level by the UART implementation (e.g., how much timing margin it has around the nominal sampling point). For lower-speed interfaces like RS-232 there is usually plenty of margin. A general guideline would be to keep total jitter to less than 25% of the bit period for a given baud rate.

    Max
  • Thanks, Max!

    It's really helpful for me!

    Regards,
    Ken