Hello e2e Ethernet Forum, we have been using the DP83848J ethernet PHY for a number of years. We have been connecting the thermal pad under the QFN to the ground layer and bottom layer through a number of vias. I am not sure this is completely necessary, but I am unable to find documentation to guide the thermal layout requirements. I have checked the datasheet, AN-1469, and SPRA953C.
Do you have a thermal layout guide for this device?
This is a top layer footprint showing (9) vias under the package. I think this might be overkill…
Thank you.
