DS25BR440: how to properly buffer lower speed LVDS clock when using DS25BR440

I have a design using 4 lanes of LVDS data at 900Mhz, along with an LVDS clock of 148.5Mhz.  This output is coming from the TI SN65DSI85 DSI to LVDS converter.  On the receive end, at my display, I want to use a DS25BR440 as a four lane equalizer.  My question is, now what do I do with the LVDS clock?  If I use the DS25BR440 there will be a 400ps prop delay that will skew the data from the clock.  What sort of part should I use to try to balance the skew here and maybe even add some EQ functionality to the clock receive end?

I looked at parts like the ds15ea101 (didn't see prop delay in datasheet), or the DS25BR110 (350ps prop delay but maybe not intended for such a low frequency).  But then I figured you must have run across this before and might have a suggestion.

Thank you