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TPD5S115: TPD5S115 DDC Unwanted Waveform

Shu-Cheng LIN
Guru 11785 points
Part Number: TPD5S115

Hi Sirs,

Sorry to bother you.

We see the unwanted waveform on HDMI DDC when we perform the test of HF1-55. This unwanted waveform will cause the faliure on "Hold time START condition" and "Setup time START condition" when we do the test by DDC Slave EDID Emulator.

DDC waveform

DDC Waveform.xlsx

The specification is

1) Hold time (repeated) START condition (tHD,STA) >= 4.0us
2) Setup time (repeated) START condition (tSU,STA) >= 4.7us

 

We see this unwanted waveform when HDMI cable plugged. This unwanted waveform presents randomly. Sometime we don't see this unwanted waveform when HDMI cable plugged. 

 

We capture some waveforms in the attached spreadsheet for your reference.

 

Waveform-1 ( 1.8V APQ side)

Unplug the HDMI monitor cable and turn on the system by monitoring HDMI_DDC_DATA, HDMI_DDC_CLK & VREG_S4A_1P8. We don't see any transition on data & Clk line.

 

Waveform-2 ( 5V HDMI side)

Unplug the HDMI monitor cable and turn on the system by monitoring HDMI_DDC_DATA_CONN, HDMI_DDC_CLK_CONN & HDMI_5V. We don't see any transition on data & Clk line.

 

Waveform-3 ( 5V side)

1. Unplug the HDMI monitor cable, allow the system to boot completely.

2. Plug the HDMI cable by monitoring HDMI_HPD_CONN , HDMI_DDC_DATA_CONN, HDMI_DDC_CLK_CONN & HDMI_5V . ( trigger at HDMI_HPD_CONN goes high from low).

 

Waveform-4 ( 1.8V side)

1. Unplug the HDMI monitor cable, allow the system to boot completely.

2. Plug the HDMI cable by monitoring HDMI_HOT_PLUG_DET, HDMI_DDC_CLK, HDMI_DDC_DATA & VREG_S4A_1P8 ( trigger at HDMI_HOT_PLUG_DET goes high from low).

 

Waveform-5 ( both 5V & 1.8V side)

1. Unplug the HDMI monitor cable, allow the system to boot completely.

2. Plug the HDMI cable by monitoring HDMI_HOT_PLUG_DET, HDMI_DDC_DATA_CONN, HDMI_DDC_DATA & VREG_S4A_1P8 ( trigger at HDMI_HOT_PLUG_DET goes high from low).

 

Could you advise your comments? How to remove this unwanted waveform?

 

  • 0
    TI__Mastermind 25880 points
    Waveform-1 ( 1.8V APQ side) and Waveform-2 ( 5V HDMI side)

    The TPD5S115 has a VIL requirement of 0.082*VDDA, so it will not function with the VIL configuration show. If VIL is not met for the part, then the level shifter will not pass data.

    Waveform-3 ( 5V side), Waveform-4 ( 1.8V side), Waveform-5 ( both 5V & 1.8V side)

    What has been driven on the SCL_B and SCL_A side of the bus. This appears to be a driven signal from the connector side of the system. The TPD5S115 is a fairly basic level shifter, so it will pass any glitch to the appropriate bus. You will need to figure out which side of the level shifter is driving the glitch. Based on what I see on the waveforms, it looks to be driving by the connector side of the DDC connection because the Waveform-5 capture shows a glitch that does not reach all the way to ground.
  • 0 in reply to Chuck Branch
    Guru 11785 points

    Hi Sirs,

    Thanks for your reply.

    We try to cut the DDC traces between APQ and TI TPD5S115 and fake the HDMI_HPD_CONN to high using tactile switch (instead of HDMI cable) and monitor the DDC_DATA and DDC_CLK.

    We can see this unwanted waveform on A side and B side of TI TPD5S115, but we don't see this unwanted waveform on APQ side.

    Please see the attached captured waveform.

    DDC Waveform_TI_20181207.xlsx

    We confirm this unwanted waveform from TI TPD5S115 after hot plug to high.

    Please help to check why there is this issue from TI TPD5S115.

    Does TI have the evaluation board for debugging?

  • 0 in reply to Shu-Cheng LIN
    TI__Mastermind 25880 points
    I will search for this EVM, but it has been discontinued, so it might be difficult for me to find.

    Have you tried adding a small capacitor to your switch the deglitch it? This may remove the glitch that is being passed into the TPD5S115.

    The TPD5S115 does not have any glitch filter from the 5V side to the 1.8V side of the level shifter(VDDA) so any glitch will pass through.
  • 0 in reply to Chuck Branch
    Guru 11785 points
    Hi Sirs,

    This glitch is from TPD5S115 itself, not from the 5V side (HDMI connecctor side).

    Could you advise where to add the small capacitor ? SCL_B and SDA_B ?
  • 0 in reply to Shu-Cheng LIN
    TI__Mastermind 25880 points
    I am suggesting to add the capacitor to the HDMI_HPD_CONN switch to slow down the waveform coming into the part. This should reduce any coupling that is happening.

    The part has an edge rate enhancer which will drive any small capacitance on the SDA_B and SCL_B lines. I also expect that adding any capacitance to the SCL_A or SDA_A lines will cause failures in the system.

    Based on your captures, I don't see anything that would be causing the DDC lines to transition within the part, so I would like to look into coupling through the power or ground planes which is why I want to slow down the HDMI_HPD_CONN edge rate.
  • 0 in reply to Chuck Branch
    Guru 11785 points

    Hi Sirs,

    Thanks for your reply.

    We still see the unwanted waveform on DDC after we add RC to slow down the switch of the HDMI_HPD_CONN.

    Please find the result in the attached file.

    DDC Waveform_TI_20181215.xlsx

  • 0 in reply to Shu-Cheng LIN
    TI__Mastermind 25880 points
    I believe that I see a potential cause for the glitch.

    The captures that you present show that the edge rate on HPD does impact the level shifters. The DDC_CLK_CONN line level of glitch changes with edge rate.

    The LS_EN signal is utilized to turn off the I2C buffers when the cable is disconnected. The buffers should be glitch free, but this is a possible cause.

    I am assuming that you followed TI's recommended routing for the LS_EN signal and it is shorted to HDP_B in copper, so the experiment of connecting LS_EN to 5V is not possible.

    The other idea I have is to put a large pull-up resistor of 50K on each of the SCL_A and SDA_A pins to see if this corrects the glitch by biasing the buffers high upon power up.

    Regards,
    Chuck
  • 0 in reply to Chuck Branch
    Prodigy 40 points

    Dear Chuck

    Currently we refer to the typical system diagram which is in the TPD5S115 datasheet. We connect LS_OE to HPD_A.

    Regarding to a large pull-up, should we connect "SCL_A and SDA_A to VCCA" or "SCL_B and SDA_B to 5V_OUT" ?

    Thanks

    Clement Tsai

  • 0 in reply to Clement Tsai
    Prodigy 40 points

    Dear Chuck

    We try to add a pull-up resistor of 50K ohm on each of "SCL_A and SDA_A to VCCA" and "SCL_B and SDA_B to 5V_OUT". We still see the glitch.

    Please see the attached file.

    F458 DDC Waveform_TI_20181218.xlsx

    Do you get the EVM and check this issue on the EVM ?

    Thanks

    Clement Tsai

  • 0 in reply to Clement Tsai
    TI__Mastermind 25880 points
    Clement,

    I am trying to find a board that I can use to evaluate this issue, there is no EVM available for this part, so I am working to find an internal board. I haven't had success with this yet.

    The SCL_B and SDA_B resistors have no impact on the results. From your waveform, it does appear that the SCL_A and SDA_A resistors reduce the glitch, but do not resolve it.

    Is it possible to try 10K resistors on the SCL_A and SDA_A lines. I do not want to go too small on these resistors because of the extremely tight VIL requirements of this part.

    Regards,
    Chuck
  • 0 in reply to Chuck Branch
    Prodigy 40 points

    Dear Chuck

    We had done the experiment to add 10K resistors on SCL_A and SDA_A before we rise this issue, but we still see the glitch.

    BTW, this glitch presents randomly. Sometime we don't see this glitch when HDMI cable plugged.

    Thanks

    Clement Tsai

  • 0 in reply to Clement Tsai
    TI__Mastermind 25880 points
    Clement,

    I have followed up with some internal teams and we did not see any type of glitch during characterization and have not had other customers have a similar experience.

    I suspect that the resolution to this issue will be to put an RC delay to the HPD_B pin vs the LS_OE pin to enable the level shifter before the HPD_B pin transitions. This will allow the level shifter to power up faster and is likely to resolve your issue.

    I realize that there is likely no way to show this will work without a PCB change because the pins are likely shorted on your board.

    I am still looking for a board to work with.

    Regards,
    Chuck
  • 0 in reply to Chuck Branch
    Prodigy 40 points

    Dear Chuck

    Thank you for the comments.

    Today we got a new board which refers to Figure 16 in TPD5S115 datasheet to connect LS_OE with one GPIO due to Vcecc issue.

    https://e2e.ti.com/support/interface/f/138/t/746111

    We won't see the glitch on the new boards.

    We do a experiment which is LS_OE going from low to high. We will see this glitch.

    From this experiment, we know this issue from the LS_OE going from low to high, and we resolve this issue on our new board.

    We can close this issue.

    Thanks

    Clement Tsai

  • 0 in reply to Clement Tsai
    TI__Mastermind 25880 points
    Clement,

    I am glad you were able to get this issues resolved. Please click the customer resolved button on the e2e email you receive.

    Regards,
    Chuck