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DP83848J: Power up Reset X1 clock requirements.

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Replies: 3

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Part Number: DP83848J

Hi,

A question on the DP83848J chip.

Q: Is it required that the X1 25 MHz clock is started/applied within a specific time period after the PHY chip is powered up?

In our case the X1 clock is applied after approx. 3 seconds after that the PHY chip is powered up.
After that the X1 clock is applied on to the PHY chip we implement a delay of 256 ms before starting/applying the MDC (preamble) to the PHY chip.

This works without any problem most of the time the system is powered on.
But , at about a frequency of one of ca 100 system (PHY chip) power up's the MII interface of the PHY chip is not working, at the next power of the PHY chip the MII interface is working, and so on.
When the X1 clock is applied at the same time the chip powered on  this problem does not occur.

Thanks
Jan

  • Hi Jan,

    Reference clock needs to be applied right at power-up.
    Could you try and hold INT/PWDN pin LOW until you apply the external clock and only release the pin when there is a clock?
    Please let me know if this eliminates the issue.

    Best regards,

    Ross Pimentel

    Ethernet - Applications Engineer

  • In reply to Ross Pimentel:

    Hi Ross,

    There is no INT/PWDN pin on the DP83848J chip as i can notice.
    I suppose you mean the "RESET_N" pin?

    Best regards
    Jan
  • In reply to Jan Lundgren41:

    Hi Jan,

    Yes, that is my mistake. Please hold RESET_N LOW until the clock is available.
    Let me know if that helps resolve the occurrence.

    Best regards,

    Ross Pimentel

    Ethernet - Applications Engineer

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