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TLK10034: 10G Base-KR AUTO NEGOTIATION is not getting completed with External Switch.

NARENDAR REDDY VYR
Prodigy 100 points
Part Number: TLK10034

Hi,

In our design we have used TLK10034 in (XAUI <-->10G Base-KR mode), 4x 10G Base-KR channels are connected to an External Switch (residing on the same PCB). 4x XAUI channels are connected to a XAUI switch. The 4x XAUI channel links are UP. But 10G Base-KR side link is not UP. Auto Negotiation is not completing with value of AN_STATUS register (0x7.0x1) toggling between 0x88 and 0xCD .The Auto Negotiation is not completed on the Link Partner side also.

What might be causing this?

  • 0
    TI__Guru 64326 points
    Narendar,

    Could you help me understand your system by providing a simple block diagram? What external switch are you using ?
  • 0 in reply to Malik Barton57
    Prodigy 100 points

    Hi Malik Barton,

    Please find the 10G Base-KR data path block diagram.

    We are using Jaguar-2 VSC7468 L2 Switch.

  • 0 in reply to NARENDAR REDDY VYR
    TI__Guru 64326 points
    Narendar,

    Is the HS_PLL_LOCK bit toggling as well? Is this a optical application? Can you confirm that the Base Page and all Next Pages are sent and received? Have you tried resetting auto-negotiation during test, using AN_RESET, when toggling is seen? Can you confirm that the Link Partner is coming up in Auto-Negotiation Mode?
  • 0 in reply to Malik Barton57
    TI__Guru 64326 points
    Hi Narendar,

    Is there any more support needed for this issue? If so please reply with any relevant details so that I can further assist you. For now I will be marking this thread as "TI Thinks Resolved". If you have resolved your issue, please post the solution to the original problem/post for others with similar issues.
  • 0 in reply to Malik Barton57
    Prodigy 100 points

    Malik Barton57,

    In continuation to my query, below are my observation.

    ON the PHY Side:

    1. After the configuration of the Link Partner Device(Jaguar2 Switch< Microsemi>), We see the following changes in the registers if the TLK device.

    a) Device Address : 0x1E Register Address : 0x0x000F

    In the register, the Value toggles between, 0x3003/0x1003/0x1803

    b) Device Address : 0x07 Register Address : 0x0x0001

    In the register above, the value toggles between 0x88/0xCD/0x8D

    c) Device Address : 0x01 Register Address : 0x0x0097

    In the register above, the value toggles between 0x4/0x6/0xC

    d) Device Address : 0x07 Register Address : 0x0x0030

     In the register above, the value toggles between 0x0011/0x0001

    Our observation is AN_COMPLETE bit is never set during the course of our observation. 

    ON the SWITCH Side(Link Partner):

     I have observed that in the Switch Training register DME Violation Bit is set and Loss of training frames lost bit is set. 

    Also, I have seen that 10G-KR negotiation bit is toggling in Switch also. 

  • 0 in reply to NARENDAR REDDY VYR
    Prodigy 100 points

    Hello Malik, any updates on this?

  • 0 in reply to NARENDAR REDDY VYR
    TI__Guru 64326 points
    Narendar,

    It seems that the Auto-Negotiation process is falling out between TLK10034 and LP due to a LOS condition. Loss of signal detection is based on the input signal level. When HSRXAP/N has a differential input signal swing of ≤65 mVpp, LOSA will be asserted (if enabled). If the input signal is greater than 175 mVp-p, LOS will be de-asserted. Outside of these ranges, the LOS indication is undefined. Once the AN process has fallen out the process will restart which i believe is the cause for the toggling. Could you verify the HS signals between TLK10034 and LP are correct/appears as excepted?
  • 0 in reply to Malik Barton57
    Prodigy 100 points
    Hi Malik Barton,
    We measured HSRXAP/N signals on scope using Active Differential probes and we are getting around 750 mVpp. We don't see the LOS condition.
    One more input is, we have used the 10G Base-KR links for connecting on Board Devices, the trace lengths are in the range of 2800mils-4700mils(for all four 10G Base-KR links) .Is there any condition that 10G Base-KR has to meet certain minimum trace length?
    Thank you.
  • 0 in reply to NARENDAR REDDY VYR
    Prodigy 100 points
    Hi Malik Barton,
    Any insights on our problem above?
  • 0 in reply to NARENDAR REDDY VYR
    Prodigy 100 points
    Hello,
    Can I know if there can be anymore help from TI regarding this issue?
  • 0 in reply to NARENDAR REDDY VYR
    TI__Guru 64326 points

    Hi Narendar,

    Unfortunately we are limited in the support provided for this device issue. I can say that the toggling is caused by link drop in auto negotiation. Device appears to be reporting LOS condition which is only possible if the criteria in the data sheet are met.

  • 0 in reply to Malik Barton57
    Prodigy 100 points
    Hi Malik Barton,
                    Some more updations &  observations regarding 10G base KR with 10GKR auto-negotiation happening at Jaguar2 chip side(L2 Switch.i.e LP).
    =======================================================
    We have started vitesse appln and 4 x 10GbaseKR interfaces were configured. We gave a reset to TI device and 10GKR auto-negotiation is completed at the Jaguar2 chip side(L2 Switch.i.e LP). The observation of AUTONEG register and training registers are compiled in the excel sheet for your information which is attached with this mail.
    LP_ADV registers at TI PHY device is not getting updated and here is the dump below.
    JR2 register dump :  Auto neg  registers set LD_ADV  & LP_ADV
    XGKR1[0]:LD_ADV:KR_7X0010 0x00001001
    XGKR1[0]:LD_ADV:KR_7X0011 0x00000000
    XGKR1[0]:LD_ADV:KR_7X0012 0x0000c000
    XGKR1[0]:LP_BASE_PAGE_0:KR_7X0013 0x00005361
    XGKR1[0]:LP_BASE_PAGE_1:KR_7X0014 0x00000083
    XGKR1[0]:LP_BASE_PAGE_2:KR_7X0015 0x0000c000
    TI-10GbaseKR PHY device register dump:   LD_ADV & LP_ADV.

    0X0007 10 0X1001 R/W 0X1001
    0X0007 11 0X0080 R/W 0X0080
    0X0007 12 0X4000 R/W 0X4000
    0X0007 13 0X0001 RO 0x0001
    0X0007 14 0X0000 RO 0X0000
    0X0007 15 0X0000 RO 0X0000


    why is register 0x13, 0x14, 0x15 not updated on TI PHY with JR2 LD_ADV values. ?
    Any hints of 10G KR AUTONEG register settings to be done at both ends so that 10gkr autoneg completes at TI PHY side also?

    I think, if this happens, autoneg process will be completed followed by link training and link UP.
    Any suggestions regarding solving this issue is welcome.
    [NOTE: Attaching excel sheet of all relevant register dumps along with data sheet]
     
  • 0 in reply to NARENDAR REDDY VYR
    Prodigy 100 points

    Hi Malik Barton,

    We were able to make the link up.We have set  "KR_TRAINING_ENABLE" bit  .i.e. Bit 1 to "0"(Device Address: 0x01, Register Address: 0x0096, Value: 0x0000 , Disable 10GBASE-KR start-up protocol ).

    Then the 10G Base-KR Link started coming-up.

    Some times we may need to give data path reset .i.e. make Device Address: 0x1E, Register Address:0x000E , Value:0x0008. We have to check whether we really need to give data path reset after disabling of KR Training.

    Thank you.