TMDS181: 1/4 Rate Clock with 4k60 Resolution

Don Schelle

Part Number: TMDS181

Hello,

I’m having a problem with the TMDS181 and looking for a little help. My problem is very similar to these two threads:

We are seeing an issue with the TMDS181 as a sink device where it does pass through the clock properly after hotplug of Quantum Data 780E Multi-Protocol Analyzer/Generator set to 3480x2160p60 (RGB bit). Firmware on the 780E has been confirmed as up-to-date (v18.08.3163).

We can scope the clock going to the IN_CLKp/n pins is 148.5 MHz, but the clock coming out of OUT_CLKp/n is 37.125 MHz. For reference we are not using the lane swap feature.

If we do any of the following, the clocks on the input and output both become 148.5 MHz and video is passing correctly:

Change the 780E video source to 4k30 and back to 4k60.
Write a 1 to APPLY_RXTX_CHANGES.
Write a 1 followed by a 0 to HPDSNK_GATE_EN.
Write a 1 followed by a 0 to PD_EN.

With regard to methods 2, 3, and 4; they all disrupt the video and can’t be pinged on a regular basis.

Our I2C_EN/PIN is tied high for I2C control and we write to register 0x0B with 0x1A on power up to set the TX_TERM_CTL to 75Ω to 150Ω.

We have used the analyzer to check that bit 1 of address 0xA8 offset 0x20 in the SCDC register set is written with a 1’b1 when the cable to the 780E is connected, we can also verify this on our receiver, and when we read back the status of register 0x0B, it shows 0x1A, which should mean the TMDS_CLOCK_RATIO_STATUS is correct on the TMDS181 and on our receiver.

Also, we’ve dumped the entire 256 byte I2C register map, in a known good and known bad state. Both maps match each other.

Our system looks like this:

HDMI Connector -> TMDS181 -> FPGA (TMDS lines)
TMDS181 (Local I2C Port) -> CPU

TMDS181 Top Marks

TMDS181
TI831
CDG7 G4

Given our system we are looking for the following:

A register bit or configuration that avoids putting the clock into this state.
A way to reliably detect if the TMDS181 is in this state through the local I2C port, at which point we can toggle the APPLY_RXTX_CHANGES bit to reset the state machine.
Some kind of hardware fix. While we can spin the board, this is the least desirable option.

Looking forward to your response.

Don

over 5 years ago

0 David (ASIC) Liu over 5 years ago

TI__Guru*** 139835 points

Don

Are you toggling HDP_SNK after hot plugging the Quantum Data 780E Multi-Protocol Analyzer/Generator?

Would you please read TMDS_CLOCK_RATIO_STATUS bits after hot plugging the generator?

Thanks
David

0 Chris Tobey over 5 years ago in reply to David (ASIC) Liu

Prodigy 20 points

Hi David,

The HPDSNK_GATE_EN is toggled after plugging in the source.
The TMDS_CLOCK_RATIO_STATUS bit shows that it is in 1/40th mode. The SCDC register on the downstream HDMI receiver also reports this bit was set correctly.
Before and after setting the APPLY_RXTX_CHANGES all registers report the same values when we read them from the TMDS181.

0 David (ASIC) Liu over 5 years ago in reply to Chris Tobey

TI__Guru*** 139835 points

Chris

Besides the HPDSNK_GATE_EN bit, have you tried to toggle the HPD_SNK pin?

The problem could be that the data are already running when hot plugging, and before the TMDS_CLOCK_RATIO bit gets set to enable 1/40 mode. If this is the case, then TMDS181 will try to adjust to a 1/40 ratio by slowing down the clock instead of keeping the clock rate the same and increasing the data rate. This problem can be resolved by causing the receiver clock detect to restart using HPD_SNK toggle, setting Apply_rxtx_change bit, or setting the PD_EN bit.

But once the receiver clock detect is restarted, it should then work properly.

Thanks
David

0 Chris Tobey over 5 years ago in reply to David (ASIC) Liu

Prodigy 20 points

Hi David,

We did try toggling the HPD_SNK pin, but it has no effect. We can see the hotplug status on the source, and can see the toggle occur. We see that this does not fix the issue.

0 David (ASIC) Liu over 5 years ago in reply to Chris Tobey

TI__Guru*** 139835 points

Chris

Can I please take a look at your schematic? For now, when hot plugging, please setting the Apply_rxtx_change bit or the PD_EN bit.

Thanks
David

0 Don Schelle over 5 years ago in reply to David (ASIC) Liu

TI__Expert 4150 points

Thanks David,

We can set the APPLY_RXTX_CHANGE bit, but we don't know when a hot-plug could occur (by definition). Is there any way that the TMDS181 can detect this?

Don

0 David (ASIC) Liu over 5 years ago in reply to Don Schelle

TI__Guru*** 139835 points

Support through direct email.

Thanks
David

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TMDS181: 1/4 Rate Clock with 4k60 Resolution