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SN65DSI84: Asking for the SN65DSI84 questions

Part Number: SN65DSI84
Other Parts Discussed in Thread: SN65DSI85, DSI-TUNER

Asking for the SN65DSI84 questions


Hi Team,

We started to bring up SN65DSI84 1 week ago.
Unfortunately, it is not successful to power on so far.
And, I found some question about power on sequence.
1. From recommended initialization sequence, all DSI input lanes including DSI CLK must be driven to LP11 state.
I’m afraid that our DSI only can output LP11 for DSI data lanes and DSI CLK keeps HS state. It doesn’t meet its requirement.
But, I checked recommended initialization sequence in SN65DSI85’s spec. It accepts DSI CLK in HS state and DSI data lanes in LP11 state.
Could we refer SN65DSI85’s initialization sequence shown below to bring up SN65DSI84?
txn.box.com/.../cwc1fe6syv6i50xi8qlvi3uiy1qo2ieo


2. From init seq1 to init seq4, all DSI input lanes including DSI CLK must be driven to LP11 state.
However, from figure 6, the drawing doesn’t meet from init seq2 ~4. Please help to check it again.
txn.box.com/.../uk2lh8osbn09p2fuvl48bz96ydqr7njg

BR,
SHH

  • Hi Scott,

    It looks like you may be referencing the old initialization sequence from before it was updated last year. The initialization sequence for both the DSI84 and DSI85 are the same, and are what you linked in your question number 1. Namely, the DSI CLK must be in HS state before EN is asserted and stay in the HS state the entire time, while the DSI data lanes must be driven to LP11 state before EN is asserted. So, it looks like your processor does meet the requirements.

    For your question number 2, that figure is from the old initialization sequence, and is no longer valid. It is also no longer in the datasheet: www.ti.com/.../sn65dsi84.pdf

    Regards,
    I.K.
  • Hi

    Continue the question of the power on sequence.

    If we use MIPI CLK as the LVDS output clock, should PLL_EN_STAT (0x0A_7) be set as 1?

    or it doesn't matter?

    BR,

    Wilbur.  

  • Hi Wilbur,

    You can't use the MIPI CLK as the LVDS output clock. You can only use it to source the PLL that generates the LVDS CLK. The PLL is something that will always need to be enabled.

    Regards,
    I.K.
  • Hi I.K.,

    I followed the power on sequence of SN65DSI84. However, there is still no display on the screen. The error information of 0xE5 register is 0x51. 

    Below is the related information.

    1. Setting information

    2. Registers

    0x09 0x00
    0x0A 0x05
    0x0B 0x28
    0x0D 0x00
    0x10 0x26
    0x11 0x00
    0x12 0x59
    0x13 0x00
    0x18 0x6f
    0x19 0x00
    0x1A 0x40  (Tunner generates 0x03 for this register, but we need to swap even / odd LVDS and select 100ohm for differential termination)
    0x1B 0x00
    0x20 0x80
    0x21 0x07
    0x22 0x00
    0x23 0x00
    0x24 0x00
    0x25 0x00
    0x26 0x00
    0x27 0x00
    0x28 0x21
    0x29 0x00
    0x2A 0x00
    0x2B 0x00
    0x2C 0x16
    0x2D 0x00
    0x2E 0x00
    0x2F 0x00
    0x30 0x05
    0x31 0x00
    0x32 0x00
    0x33 0x00
    0x34 0x4a
    0x35 0x00
    0x36 0x00
    0x37 0x00
    0x38 0x00
    0x39 0x00
    0x3A 0x00
    0x3B 0x00
    0x3C 0x00
    0x3D 0x00
    0x3E 0x00

    The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

    3. Waveforms

    Please help to check if something is wrong. 

    BR,

    Wilbur.

  • Hi Wilbur,

    The initialization looks okay. However, you have a line time mismatch in the outputs window of the DSI-Tuner. The LVDS line time is 14.411 while the DSI line time is 14.814. These needs to be the same since the DSI84 doesn't realign timing.

    To fix this, you should change the "LVDS_HFP" parameter to 44 (half of the "DSI_HFP" parameter). Right now you have it set to 14.

    Also, are you able to get the test pattern to display? You can check the box in the DSI-Tuner to get the settings for it.

    Regards,
    I.K.
  • Hi A.I., 

    I corrected the LVDS_HFP to 44. 

    1. The outputs are same as what you said.

    2. However, I don't see any different setting from CSR.txt file. Is it correct?

    0x09 0x00
    0x0A 0x05
    0x0B 0x28
    0x0D 0x00
    0x10 0x26
    0x11 0x00
    0x12 0x59
    0x13 0x00
    0x18 0x6f
    0x19 0x00
    0x1A 0x03   --> We use 0x40
    0x1B 0x00
    0x20 0x80
    0x21 0x07
    0x22 0x00
    0x23 0x00
    0x24 0x00
    0x25 0x00
    0x26 0x00
    0x27 0x00
    0x28 0x21
    0x29 0x00
    0x2A 0x00
    0x2B 0x00
    0x2C 0x16
    0x2D 0x00
    0x2E 0x00
    0x2F 0x00
    0x30 0x05
    0x31 0x00
    0x32 0x00
    0x33 0x00
    0x34 0x4a
    0x35 0x00
    0x36 0x00
    0x37 0x00
    0x38 0x00
    0x39 0x00
    0x3A 0x00
    0x3B 0x00
    0x3C 0x00
    0x3D 0x00
    0x3E 0x00

    The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

    3. The circuit board is made by us. If I want to get the test pattern to display, the only thing that I need to do is to get the setting from DSI-Tunner. Should I need to modify anything else? (Ex: LVDS_CLK source)

        I'll do it today and get back the result to you.

    BR,

    Wilbur.

        

  • Hi Wilbur,

    Yes that's fine. What's important is that your DSI source is actually outputting the blanking parameter values you entered into the DSI-Tuner DSI_Inputs window. Some of the LVDS settings are for test pattern generation so they won't change unless the test pattern is enabled, but it's good practice to enter the values correctly so that the line time matches between the LVDS side and the DSI side in the Outputs window.

    For the test pattern, yes the only thing you need to do is get the settings from the DSI-Tuner when the "Test Pattern" box is checked. No DSI data is received in test pattern mode, so you only need the DSI CLK.

    FYI, the test pattern should look like the below:


    Regards,
    I.K.

  • Hi A.I.,

    From your message, I think that the MIPI source is non-burst mode and horizontal blanking is half as panel requirement. 

    There should be something wrong in the MIPI output chip before SN6DSI84.

    So, I changed the mode to Burst mode and got a good result. 

    PLL is locked successfully. LVDS  data and clock is outputting, too. The LVDS data seems the data for color bar. 

    However, the MIPI clock that I measured is 545MHHz, It should be 445.5MHz. That should be why the display can't be brought up.

    545/445.5=1.22 --> It seems that it multiplys 1.22 for Burst mode. 

    Sorry that I'm not really know DSI burst mode. 

    Do you have any suggestion how to set DSI_inputs for this kind of Burst mode?

    BR,

    Wilbur.

  • Hi Wilbur,

    Yes that frequency is much too fast. You will need to consult with whomever manufactures your DSI source to get support with modifying the DSI parameters. I can only help with the DSI84 settings, and the DSI84 has no settings for burst/non-burst mode as it will just bridge whatever is on the input.

    Regards,
    I.K.
  • Hi I. K.,

    The panel was brought up successfully to display the test pattern after modifying the input DSI frequency less than 500MHz.

    However, there is still one question about the setting of CHA_DSI_CLK_RANGE.

    The real DSI frequency is set to 490.05MHz because it's set to multiplys 1.1 for Burst mode. (445.5MHz*1.1=490.05MHz)

    So, either 0x59(445.5MHz) or 0x62(490.05MHz)  should I set for CHA_DSI_CLK_RANGE (address: 0x12)? 

    1. Tooling setting (DSI frequency = 445.5MHz)

    2. Tooling setting (DSI frequency = 490.05MHz)

    BR,

    Wilbur.

  • Hi Wilbur,

    If the DSI CLK frequency going into the DSI84 is 490.05 MHz then the device should be configured as such. One issue with this frequency, though, is that there is a line time mismatch between the LVDS side and the DSI side, as you can see from the outputs window.

    The line time on the LVDS side is 14.815us while the line time on the DSI side is 13.468us. So, the DSI CLK is significantly fast enough to enable DSI data to complete an entire line (from hsync to hsync) faster than the LVDS side can. This is fine for the test pattern since no DSI data is used, but it is problematic for actual DSI streaming.

    To remedy this you have 2 options:

    1. Use a faster LVDS CLK to make the line time match the DSI side. In this case you would need exactly 81.675MHz LVDS CLK:

    For this you would also need to ensure that this frequency is within specification of your display datasheet.

    2. Add more blanking to the DSI side to make the line time match the LVDS side. You would need to add 220 pixels to one of the blanking parameters (or split the 220 among all 3, it doesn't matter as long as you add 220 total blanking pixels) on the DSI side. Ensure your DSI source is actually outputting these parameters. 

    The numbers above come from manipulating equations (2) and (5) in this application note: http://www.ti.com/lit/an/slla356/slla356.pdf

    Regards,

    I.K.