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  • TI Thinks Resolved

TDP158: Details of pins

Intellectual 640 points

Replies: 5

Views: 160

Part Number: TDP158

Hi,

I want to use this IC for the HDMI purpose in the pin strapping mode.

I have following doubts:-

1. SoC side my voltage for DDC signals is 1.05V. I am using the LT which convert 1.05V to 3.3V.

Can I use this topology
SoC(1.05V) <--> LT(1.05 to 3.3V) <--> TDP158 <--> HDMI connector.
The doubt came as the datasheet suggest to use  below topology ( datasheet Figure 46)
SoC(1.05V) <--> LT(1.05C to 5V) <--> HDMI connector.

2. I want to understand the use of SWAP pin.I am not clear as it mention in the datasheet.

3. I will using this IC in pin strapping mode. I want to understand the pin fumctionality of EQ1/A0 and EQ1/A1 pins

Thanks

Ash

  • Ash

    1a. The TDP158 uses clock stretching for DDC transactions. As there are sources that does not support this function, a system may not work correctly as DDC transactions are incorrectly transmitted/received. To overcome this, a snoop configuration can be implemented where the SDA/SCL from the source is connected directly to the SDA/SCL of the sink. The TDP158 needs the SDA_SNK and SCL_SNK pins connected to the sink DDC pins so that the TMDS_CLOCK_RATIO_STATUS bit can be automatically set. For best noise immunity, the SDA_SRC and SCL_SRC pins should be connected to GND. Care must be taken when this configuration is being implemented as the voltage level for DDC between the source and sink may be different, 3.3 V vs 5 V.

    1b. With HDMI connector, there will be devices that have 5V DDC, so you do need 1.05V to 5C level shifter.

    2. Please refer to section 8.3.4 of the datasheet

    3. Please refer to section 8.3.6 of the datasheet, EQ2/1 setting are depending on the insertion loss of the system.

    Thanks
    David
  • In reply to David (ASIC) Liu:

    thanks a lot david..

    I have one more doubt

    The ramp up time between 3.3V and 1.1V is max 200uS ? Also there is VDD and VCC ramp as max 100ms.
    can you clarify?How come between the VCC and VDD only 200us maximum time difference.
  • In reply to johnn:

    Ash

    200us is the time VCC needs to be stable before VDD.

    So VCC ramps up with max 100ms. Once VCC is stable, VDD ramp up, VDD needs to ramp within 200us, and with max 100ms ramp up time.

    Thanks
    David
  • In reply to David (ASIC) Liu:

    HI David thanks..Can you please help me on i2c address of this device?
  • In reply to johnn:

    Ash

    When in pin strap mode (i2c_en = low), A0/EQ1 and A1/EQ2 are EQ1 and EQ2. You need to set the EQ depending on your system channel loss (Table 3 of the TDP158 datasheet).

    When in i2c mode (i2c_en = high), A0/EQ1 and A1/EQ2 are A0 and A1. The can be set either high or low to program different i2c address (Table 6 of the TDP158 datasheet).

    Thanks
    David

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