DP159RGZEVM: How to use it with two lane interface for DisplayPort application

Bhushan Patil1

Part Number: DP159RGZEVM

Hello All,

Q.1. Is it possible to reduce no of lanes of DP159 on hardware schematic for DisplayPort Application? By default this connection is 4 lanes, we want to reduce it to two lanes.

Q.2. If yes, does clock lane connection is compulsory? (i.e. IN_CLKp and IN_CLKn connection to ). If connect two data lane will it work?

Q.3 Which register setting need to be changed in such case?

Thank you in advance.

Regards,

Bhushan

over 4 years ago

0 David (ASIC) Liu over 4 years ago

TI__Guru*** 139515 points

Bhushan

You can design DP159 with 2 DP lanes as shown in your block diagram.

Please refer to section 4.2 of this app note: www.ti.com/.../slla358.pdf.

The source tells the sink the number of lane being supported, and then sink programmed the DP159 to the appropriate number of lane.

Can you please share more detail of your application?

Thanks
David

0 Bhushan Patil1 over 4 years ago in reply to David (ASIC) Liu

Prodigy 60 points

Hello David,

Thank you for your prompt reply.
We have connected 2 lanes in our design from DP connector to DP159 and providing this signals to FPGA.
AUX_SRCP and AUX_SRCN signals generated from DP159 is further provided to clock of DisplayPort RX PHY section.
We are not getting this clock correctly. So, we are not able to capture DP signals correctly.

Objective is to receive 4k 2160p resolution with 16fps.

0 David (ASIC) Liu over 4 years ago in reply to Bhushan Patil1

TI__Guru*** 139515 points

Bhushan

Are you following section 4.5 of this app note: www.ti.com/.../slla358.pdf

Please also write 0x00b to Page 1 Addr 0x0Dh and see if there is a clock on AUX.

Thanks
David

0 Bhushan Patil1 over 4 years ago in reply to David (ASIC) Liu

Prodigy 60 points

Hello David,

Thanks once again. Your inputs are helpful. I will check it and let you know .
Last thing, I want to know about is what is default status of AUX_SRCP and AUX_SRCN signals.
Do we see any output on them?

Best Regards,
Bhushan

0 David (ASIC) Liu over 4 years ago in reply to Bhushan Patil1

TI__Guru*** 139515 points

Bhushan

AUX default is I2C over AUX. Since we don't use I2C over AUX, there should be nothing on the output of AUXP/N.

Thanks
David

0 David (ASIC) Liu over 4 years ago in reply to David (ASIC) Liu

TI__Guru*** 139515 points

Bhushan

I did not catch a mistake in your block diagram. Lane 0 has to be connected to either IN_D2 or IN_CLK in order for the clock recovery to work properly.

Thanks
David

0 Bhushan Patil1 over 4 years ago in reply to David (ASIC) Liu

Prodigy 60 points

Hello David,

If you observe carefully in my block diagram Lane 0 is not connected to IN_D2 or IN_CLK; it is connected to IN_D0.

Best Regards,

Bhushan

0 David (ASIC) Liu over 4 years ago in reply to Bhushan Patil1

TI__Guru*** 139515 points

Bhushan

In order to recover the clock, lane 0/3 needs to be connected to IN_D2 or IN_CLK.

Thanks
David

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DP159RGZEVM: How to use it with two lane interface for DisplayPort application