DP83848I-MAU-EK: DP83848I-MAU-EK/NOPB

Hi Craig,

That analogy is hilarious.

Are you trying check the PHY only or check both your verilog and the PHY together?

If you are only looking to test the PHY, if the BERT can receive the same frame back, you can just wire on the board an external loopback (i.e. RX to TX without the FPGA).

If you are looking to check the PHY + your verilog, then the method you described above is great.

Ross,

I only want to check the phy.   Here is what I have done.   I removed the 25mhz osc and put on the 50mhz.   I removed the c3,c4 and y1 and installed and populated the jumper J6 to make it only RMII mode.  I have the BERT running at 100M.    I thought I might be able to loop R1 to T1 and R0 to T0 but it doesn't seem to work that way.  

I am providing 5v to pin one on J7.   It says 3.3 but is the square pin on the bottom so think the board is mislabeled.   I am struggling as well to be able to talk to the PHY.   I was thinking I could use the usb2mdio msp430 to talk to the PHY like I normally do with the 83867 but it never seems to find the PHY ID.  Any thoughts on what I might be missing?   All I need to do is run that BERT into the PHY and loop it back to the BERT.

Craig

2388.schematics.pdf