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DP159RGZEVM: Required details of DP159 commands

Part Number: DP159RGZEVM

Hello All,

SLLA358 shows below command in 4 Initial Power-up Configuration.

{0x0D, 0x02} , //Select LN0 for clock.

What exactly it means? Does it it recovers DP sink clock from LN0?

If Lane 0 is not connected then do we need to make any changes here?

Connection details: DP RX connector LANE 0  > IN_D0 and DP RX connector LANE 1  > IN_D1

Similarly, for {0x30, 0xE0} , //Disable Receivers except lane 0

Please let me know reason for lane 0 is exception in this case. Do we need to perform any change in this instruction for our connection mentioned above?

Best Regards,

Bhushan

  • Bhushan

    Page 1 0x0Dh, bit [1:0] is the clock lane select. These two bits select between lane 0 or lane 3 as clock lane.
    0 – Lane 3 is clock lane
    1 – Lane 0 is clock lane

    Page 1 0x30h is receive control register. Bit [7:4] powers up/down RX analog block and bit [3:0] disable/enable the receiver lane.

    Thanks
    David
  • Hello David,

    Do you mean AUX_SRC output of DP159 will be generated from either lane 0 or lane 3 only?
    I am still unclear about clock terminology in this case; as per DP specification "All lanes carry data. There is no dedicated clock channel."

    For Page 1 0x30h receive control register; I am interested to know why Lane 0 is exempted.

    Thank you in advance.

    Best Regards,
    Bhushan
  • Bhushan

    You are correct that for DP, all lanes carry data and there is no dedicated clock channel. The clock in this case is the recovered clock from either lane 0 or lane 3 data.

    The DP159 app note is tied to the Xilinx FPGA design. The Xilinx FPGA requires a clock for its logic. So lane 0 is enabled first in order to provide a clock to the FPGA.

    Thanks
    David
  • Bhushan

    I made a mistake in my previous response, the bit to select between lane 0 and lane 3 is

    Page 1 0x0Eh, bit 1
    0 – Lane 3 is clock lane
    1 – Lane 0 is clock lane

    Thanks
    David
  • Thanks Bhushan, for the information.
    Can you please clarify if Lane 0 corresponds to IN_D0 pin of DP159, Lane 1 to IN_D1, Lane 2 to IN_D2 and Lane 3 to IN_CLK.

    Thanks,
    Shaji NM