Other Parts Discussed in Thread: DP83848J,
New board design uses DP83848I Ethernet PHY. Previous generation used the DP83848J PHY. Corresponding pins are connected and strapped similarly between the two designs, although DP83848I has additional pins.
On previous gen design,when board is powered-up and 25 MHz crystal is supplied to PHY, clocks can be seen on the TX_CLK and RX_CLK outputs with no controller intervention.
On new design with DP83848I, a similar power up does not result in clock outputs on TX_CLK/RX_CLK. There is a concern that something is not set correctly. The 25 MHz clock is observed on CLK_OUT pin so Ttere's confidence the crystal input is Ok even though this is a different crystal.
Are there settings we need to be aware of with the DP83848I that might be leading to this difference? Maybe one of the additional pins on the device? For example, the PWR_DOWN pin is floating as it has a weak pull-up to keep device out of power down mode.
Or must the DP83848I be written to by the controller to get the data paths in a similar state as seen with the DP83848J?
