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Original question:

DP83867IR: MDIO being pulled low

DP83867IR: Could you please share why GPIO_0 give an effect to MDIO level?

Vincent Hwang
Prodigy 100 points
Part Number: DP83867IR

Could you please share why GPIO_0 give an effect to MDIO level?

I have to explain any reason to our customer.

  • 0
    TI__Mastermind 18425 points
    HI Vincent,

    The original post that you linked is specific to an application of Xilinx SOC with DP83867. In their application, GPIO_0 might be getting strapped in mode 4 which is a restricted mode for DP83867 and should not be used for normal application.
    GPIO_0 is a boot strap pin which controls features of the PHY. Mode 4 controls a internal feature that should not be used in normal operation, which is why its is restricted in the datasheet.

    -Regards
    Aniruddha