DS280DF810: PRBS clk (DS280DF810EVM)

1. Is it possible to synthesize the synchronization frequency using the external pulse generator applied to the Rx0 input to obtain test data at the output of the Tx0 channel with a transmission rate of 28.78125, 25.78125, 10.3125 Gbps and Prbs 31?

Yes. The user simply needs to provide a 1010 clock input signal that is multiple of the programmed CDR rate. The reference input signal data rate can be as low as divide by 16.

2. What should be the topology of the connection scheme?

No special topology required. Just need a clock input signal to the channel under test. The user would then need to enable PRBS generator output on this channel.

3. What should be the frequency of the external pulse generator for these transmission rates?

If the CDR rate is set for 25.78125Gbps on the channel under test, the reference clock input signal frequency may be as low as divide by 32. This corresponds to 402.832031MHz.

Cordially,

Rodrigo Natal

HSSC Applications Engineer