This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DSI84: configuration using DSI tuner

Part Number: SN65DSI84
Other Parts Discussed in Thread: SN65DSI83, DSI-TUNER

Hi,

We are using a custom board which has MIPI DSI to LVDS bridge (SN65DSI84) to give LVDS display.

We need to bring up a dual channel LVDS display (G133HAN01.0 AUO). LVDS panel pixelclock ranges from 134 MHZ to 149 MHZ.

We have configured panel inputs and DSI inputs according to the datasheet to generate the CSR values. But we are getting a warning message "DSICLK RATE SHOULD BE LESS THAN 500M"  even though the DSI clock rate is 423 MHZ.

Attached the pictures of DSI tuner configurations for your reference.

  1. Is our configurations are correct ?
  2. Can we skip this warning message ?
  3. How can we overcome this warning message ?

Please provide your feedback.

Thanks,

Antony

  • Hi Antony,

    This is because your configuration calls for a 707 MHz DSI CLK rate to source the LVDS CLK frequency you specified and to  ensure the line time is the same on the DSI side and the LVDS side. Your configuration is not correct. Your LVDS panel probably has two clock inputs, which means the LVDS clock frequency should be half of what you specified.

    Please reference this video to understand how to configure the device correctly: https://training.ti.com/configuring-sn65dsi8x-single-channel-dsi-dual-link-lvds-operation

    Regards,

    I.K. 

  • Hi I.K,

    As you suggested, given LVDS clock frequency as 71 Mhz (142/2). Now the warning message is not coming.

    But there is no display in the LVDS panel and the pixel clock (lvds actual clock rate) is set into 74 MHZ instead 71 MHZ.

    Below is the lvds panel parameters that we are providing in dts file.

    dsi_lvds_bridge: sn65dsi84@2c {
    compatible = "ti,sn65dsi83";
    reg = <0x2c>;
    ti,dsi-lanes = <4>;
    ti,lvds-format = <1>;
    ti,lvds-bpp = <24>;
    ti,width-mm = <293>;
    ti,height-mm = <165>;
    enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
    power-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
    bklite-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
    bkliteen-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_lvds>;
    status = "disabled";

    display-timings {
    lvds {
    clock-frequency = <71000000>;
    hactive = <1920>;
    vactive = <1080>;
    hfront-porch = <58>;
    hsync-len = <42>;
    hback-porch = <88>;
    vfront-porch = <8>;
    vsync-len = <14>;
    vback-porch = <14>;
    hsync-active = <0>;
    vsync-active = <0>;
    de-active = <1>;
    pixelclk-active = <0>;
    };
    };

    port {
    sn65dsi84_in: endpoint {
    remote-endpoint = <&mipi_dsi_bridge_out>;
    };
    };
    };

    };

    1. What is the expected DSI clock frequency for the above LVDS panel parameter values?
    2. What is the expected LVDS clock frequency ?

    We got the below clock frequencies when the pixelclock value is 142 MHZ. We yet to measure for 71 MHZ pixel clock.

    DSI clock -  416 MHZ

    LVDS channel A -  139 MHZ

    LVDS channel B - 136.99 MHZ

    Is this correct for provided pixel clock 142 MHZ ? 

    Please provide your feedback.

    Thanks,

    Antony

  • Hi Antony,

    For 2x 71 MHz LVDS clock, the DSI CLK needs to be 426 MHz. 

    I'm looking at your display datasheet (https://www.distec.de/fileadmin/pdf/produkte/TFT-Displays/AUO/G133HAN01.0_Datasheet.pdf) and it looks like they did not describe the timing characteristics very well. Since it's a dual LVDS panel, all of the horizontal parameters (active pixels, blanking pixels, clock frequency) need to be divided by 2. Normally the datasheet does that for you but this one does not. 

    Namely, 

    LVDS_HPW = 21

    LVDS_HBP = 44

    LVDS_HFP = 29

    This is on the LVDS side. On the DSI side, they should be double that of the LVDS side (since it's doing single dsi to dual LVDS conversion):

    DSI_HPW = 42

    DSI_HBP = 88

    DSI_HFP = 58

    For the vertical parameters, the timing should be the same on both sides. I'm not sure why you used different values in your DSI-Tuner screenshots above. 

    LVDS_VPW = 14

    LVDS_VBP = 14

    LVDS_VFP = 8

    DSI_VPW = 14

    DSI_VBP = 14

    DSI_VFP = 8

    I have attached new settings as a .dsi file that you can try. Just import it into the DSI-Tuner and generate the settings:

    antony.dsi

    You should also ensure that the output from your DSI source (clock frequency, blanking, etc.) actually matches the settings input into the DSI-Tuner, and that you are following the initialization sequence in the datasheet.

    Regards,

    I.K.

  • Hi I.K,

    Imported antony.dsi file in DSI tuner, generated CSR values and updated the values in my driver file.

    Still I am not getting any display in LVDS.

    Below is dcss and mipi_dsi config in .dts file.Do we miss anything in dcss and mipi_dsi configuration in .dts file ?

    DCSS config:

    &dcss {
    status = "okay";
    disp-dev = "mipi_disp";

    clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
    <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
    <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
    <&clk IMX8MQ_CLK_DC_PIXEL>,
    <&clk IMX8MQ_CLK_DUMMY>,
    <&clk IMX8MQ_CLK_DISP_DTRC>;
    clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
    assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>,
    <&clk IMX8MQ_CLK_DISP_AXI>,
    <&clk IMX8MQ_CLK_DISP_RTRM>;
    assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
    <&clk IMX8MQ_SYS1_PLL_800M>,
    <&clk IMX8MQ_SYS1_PLL_800M>;
    assigned-clock-rates = <594000000>,
    <800000000>,
    <400000000>;

    dcss_disp0: port@0 {
    reg = <0>;

    dcss_disp0_mipi_dsi: mipi_dsi {
    remote-endpoint = <&mipi_dsi_in>;
    };
    };
    };

    MIPI DSI and MIPI DSI Bridge config:

    &mipi_dsi {
    status = "okay";
    assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>,
    <&clk IMX8MQ_CLK_DSI_CORE>,
    <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
    <&clk IMX8MQ_VIDEO_PLL1>;
    assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
    <&clk IMX8MQ_SYS1_PLL_266M>,
    <&clk IMX8MQ_CLK_25M>;
    assigned-clock-rates = <24000000>,
    <266000000>,
    <0>,
    <426000000>;
    sync-pol = <1>;
    pwr-delay = <10>;

    port@1 {
    mipi_dsi_in: endpoint {
    remote-endpoint = <&dcss_disp0_mipi_dsi>;
    };
    };
    };

    &mipi_dsi_bridge {
    status = "okay";

    panel@0 {
    reg = <0>;
    status = "okay";
    compatible = "auo,g133han01";
    pinctrl-0 = <&pinctrl_panel>;
    backlight = <&backlight>;
    bridge-i2c-bus = <&i2c4>;
    bridge-info = <4>;
    bridge-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
    enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
    #if useReg
    power-supply = <&reg_gpio_lvds>;
    #else
    power-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
    #endif
    dsi-lanes = <4>;
    panel-width-mm = <293>;
    panel-height-mm = <165>;

    port {
    panel_in: endpoint {
    remote-endpoint = <&mipi_dsi_bridge_out>;
    };
    };
    };

    port@1 {
    mipi_dsi_bridge_out: endpoint {
    remote-endpoint = <&panel_in>;
    };
    };
    };

    Please verify and provide your feedback.

    Below is the panel and DSI configuration :

    static int bridge_sn65dsi84_config(struct panel_simple *p)
    {
    int i=0, size=0, err=0;

    switch(p->bridge_info)
    {

    case 1:

    :

    :

    case 4: /* g133han01 */
    {
    char addresses[] = {
    0x09, 0x0A, 0x0B, 0x0D, 0x10, 0x11, 0x12, 0x13,
    0x18, 0x19, 0x1A, 0x1B, 0x20, 0x21, 0x22, 0x23,
    0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B,
    0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33,
    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B,
    0x3C, 0x3D, 0x3E, 0x0D
    };
    char values[] = {
    0x00, 0x05, 0x28, 0x00, 0x26, 0x00, 0x55, 0x00,
    0x6F, 0x00, 0x03, 0x00, 0x80, 0x07, 0x00, 0x00,
    0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00,
    0x15, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00
    ,
    0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
    ,
    0x00, 0x00, 0x00, 0x01
    };


    i = sizeof(addresses);
    size = sizeof(values);
    err = bridge_sn65dsi84_write_values(p, addresses, values, i, size);
    }
    break;

    static const struct drm_display_mode auo_g133han01_mode = {
    .clock = 71000,
    .hdisplay = 1920,
    .hsync_start = 1920 + 29,
    .hsync_end = 1920 + 29 + 44,
    .htotal = 1920 + 29 + 44 + 21,
    .vdisplay = 1080,
    .vsync_start = 1080 + 8,
    .vsync_end = 1080 + 8 + 14,
    .vtotal = 1080 + 8 + 14 + 14,
    .vrefresh = 60,
    .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
    };

    static const struct panel_desc_dsi auo_g133han01 = {
    .desc = {
    .modes = &auo_g133han01_mode,
    .num_modes = 1,
    .bpc = 8,
    .size = {
    .width = 293,
    .height = 165,
    },
    .bus_flags = DRM_BUS_FLAG_DE_HIGH,
    },
    //.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
    .flags = MIPI_DSI_MODE_VIDEO,
    .format = MIPI_DSI_FMT_RGB888,
    .lanes = 4,
    };

    Please provide your feedback.

    Thanks,

    Antony

  • Antony,

    I cannot help with your processor DSI configuration or code, only with the configuration of the DSI84.

    If you are not getting any display, there are a couple of things you can check:

    • Verify that you are following the initialization sequence in the datasheet. This is critical for correct operation of the device.
    • Make sure that your DSI CLK is continuous, and stays in HS mode the entire time after initialization
    • Ensure that the output of your DSI source matches what you are programming in the DSI84 (frequency, active pixels, blanking pixels)

    Regards,

    I.K. 

  • Hi I.K,

    We have created taken antony.dsi file which you provided. Changed the clock to 74 MHZ. SO the DSI clock now is 444 MHZ.

    We have created test pattern using this .dsi file and test pattern is displayed successfully.

    We see that for test pattern the horizontal resolution is divided by 2. (reg 0x20 = 0xc0, 0x21= 0x03  i.e 1920/2 = 960).

    The same register(0x20 and 0x21) values we tried for original CSR values (Test pattern is disabled in this case).

    But no display on LVDS.

    Please provide your feedback.

    Thanks,

    Antony

  • Antony,

    The settings I provided have the DSI CLK as 426 MHz, which corresponds to a value of 0x55 being written to register 0x12 (CHA_DSI_CLK_RANGE). If you are using these settings but changed the DSI CLK to 444 MHz, you need to write 0x58 to this register. 

    If you make any changes you need to make sure to put them in the DSI-Tuner and regenerate CSR configuration text file. You cannot just change settings on the fly. 

    If you are able to see the test pattern but no display when using actual DSI input, then there is something wrong on the DSI side with your processor. For this my feedback is the same as in my previous reply. You need to check those points.

    Regards,

    I.K. 

  • Hi I.K,

    Yes, I have generated the new CSR values after changing the DSI clock which  I forgot to mention. Register 0x12 has value 0x58.

    I also checked the three points which you suggested.

    1. Verify that you are following the initialization sequence in the datasheet. This is critical for correct operation of the device.

    • The PLL_UNLOCK bit of control status register 0xE5 is getting set. We tried clearing this bit by writing 0xff. But still the register bit is set.

    2. Make sure that your DSI CLK is continuous, and stays in HS mode the entire time after initialization

    • HS_CLK_SRC bit of control status register 0x0A is set to 1

    HS_CLK_SRC

    0 – LVDS pixel clock derived from input REFCLK (default)

    1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock

    1. Ensure that the output of your DSI source matches what you are programming in the DSI84 (frequency, active pixels, blanking pixels)
    • DSI clock frequency 444 MHZ matches with the frequency programmed in DSI tuner. Not probed, but verified using printk statement.

    Below is our initialization sequence:

    static int bridge_sn65dsi84_enable(struct panel_simple *p)
    {
    int i, err=0;
    int chipid[] = {0x35, 0x38, 0x49, 0x53, 0x44, 0x20, 0x20, 0x20, 0x01};
    char address, value;
    if (p->bridge_gpio)
    {
    gpiod_set_value_cansleep(p->bridge_gpio, 0);
    msleep(10);
    gpiod_set_value_cansleep(p->bridge_gpio, 1);
    msleep(10);
    }
    for (i = 0; i < sizeof(chipid) / sizeof(int); i++) {
    address = (char)i;
    err = sn65dsi84_i2c_read(p->bridge, &address, 1, &value, 1);
    if (err < 0) {
    printk("failed to read chip id\n");
    return err;
    }
    if (value != chipid[i]) {
    printk("chip id is not correct\n");
    return err;
    }
    }
    err = bridge_sn65dsi84_config(p);
    if( err < 0)
    return err;

    msleep(50);
    err = sn65dsi84_write_reg(p->bridge, 0x09, 0x01);
    if (err < 0) {
    printk("failed to write data to the chip\n");
    return err;
    }
    msleep(50);

    address = 0xe5;
    err = sn65dsi84_i2c_read(p->bridge, &address, 1, &value, 1);
    if (err < 0) {
    printk("failed to read chip id\n");
    return err;
    }

    msleep(500);

    return 0;

    }

    Please provide your feedback.

    Thanks,

    Antony

  • Antony,

    Please post an oscilloscope screenshot of your initialization sequence. It should look like the below:

    Also, when I said make sure that your DSI CLK is continuous, and stays in HS mode the entire time after initialization, I mean you should ensure that it does not return to LP11 mode after the initialization, and remains in HS. Is this the case? 

    Regards,

    I.K.

  • Hi I.K, 

    We have measured our initialization sequence. Please see below and provide your feedback.

    LVDS single channel : EN to DSI_DATA about 750ms (Bring up normally)

     
    LVDS dual channel : EN to DSI_DATA about 1500ms(Bring up abnormally)

    LVDS single channel : EN to DSI_DATA about 750ms (Bring up normally)
     
    LVDS dual channel : EN to DSI_DATA about 1500ms(Bring up abnormally)

  • Antony,

    Your last 2 images did not attach correctly.

    Additionally, it looks like there's a glitch on the EN pin. Note that if the EN pin is driven low, you need to wait at least 10ms before asserting it high again, or the device may not start up correctly. 

    Regards,

    I.K. 

  • Hi I.K,

    We have probed MIPI DSI signals coming out imx8m processor. From DSI tuner, suggested DSI clock is 222 MZH and DSI Ch A clock is 444 MHZ. CSR register 0x12 value is  0x58.

    Below is our oscilloscope screenshot showing DSI clock as 218 MHZ. But we are expecting 444 MHZ.

    DSI Clock frequency : 218MHz


     

    DSI data activity


     


     

    Please provide your feedback on DSI clock.

    Why it is showing 218 MHZ instead of 444 MHZ?

    Thanks,

    Antony

     

  • It's probably an issue with your processor, which is something you'd have to ask an NXP engineer for assistance with. The DSI84 does not control what is output from the processor.

    Regards,

    I.K. 

  • Hi Antony,

    Is this issue still open?

    Regards,

    I.K. 

  • Yes I.K . We are contacting NXP engineer regarding the MIPI DSI signals coming out of imx8m processor.

  • Hi Antony,

    Understood; please keep me updated with any progress or if further assistance is needed with the DSI84.

    Regards,

    I.K.