Other Parts Discussed in Thread: SN65DSI83, DSI-TUNER
Hi,
We are using a custom board which has MIPI DSI to LVDS bridge (SN65DSI84) to give LVDS display.
We need to bring up a dual channel LVDS display (G133HAN01.0 AUO). LVDS panel pixelclock ranges from 134 MHZ to 149 MHZ.
We have configured panel inputs and DSI inputs according to the datasheet to generate the CSR values. But we are getting a warning message "DSICLK RATE SHOULD BE LESS THAN 500M" even though the DSI clock rate is 423 MHZ.
Attached the pictures of DSI tuner configurations for your reference.
- Is our configurations are correct ?
- Can we skip this warning message ?
- How can we overcome this warning message ?
Please provide your feedback.
Thanks,
Antony