This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN75DP159: The output clock of SN75DP159 is not equal to the input clock

Part Number: SN75DP159

Hello

I want to use DP159 to generate TMDS signals from input data and clocks. The clock and data input of DP159 comes from the FPGA.

I found that the clock frequency of OUT_CLK output of DP159 is not equal to the clock frequency of IN_CLK input.

DP159 is set by default, I2C_EN_PIN = 1.

I don't know why. Can anyone tell me?

Regards

  • Would you please share your schematic? Any chance you can access the DP159 I2C registers and dump out the register value?

    What is the measured input and output clock frequencies? 

    Are you transmitting HDMI1.4 or 2.0? 

    Thanks

    David

  • Hi,David

    Thank you for your reply.

    I can access the DP159 I2C registers and dump out the register value. 

    I am transmitting HDMI1.4. and input clock frequency is 148.5MHz ,output clock frequency is uncertain and VOD is about 40mV.

    This is my schematic.

    regards

  • Looking at the schematic

    1. Do you have the appropriate pullup on SDA_SNK and SCL_SNK?

    2. If not used, SDA_SRC and SCL_SRC need to be pulled to GND.

    3. How does HPD_SNK being connected?

    Would you please dump out both Page 0 and Page 1 of the DP159 register? To access Page 1 register, please write 0x01 to address 0xFFh first.

    Thanks

    David

  • Hi, David

    Thank you for your reply.

    I am look at schematic and board again.

    1. SDA_SNK and SCL_SNK is pulled to VCC3V3 through 10K resistance.

    2. SDA_SRC and SCL_SRC is  only pulled to VCC3V3 through 2K resistance, and not connected other contorl Pin such as MCU.

    3. HPD_SNK have been detected by measuring voltage, HDP_SRC output voltage is 3.1V.

    I don't know where is Page 0 and Page 1 of the DP159 register and I can't found Page 0 and Page 1 in DP159 data sheet.

    But I try to access Page 1 register through write 0x01 to address 0xFFh.

    the result as follow, the value of Page 1 register is different  in twice read.

    DP159_page0_v1_1.txt
    00
    00
    00
    00
    0F
    00
    00
    00
    00
    00
    80
    00
    F0
    00
    00
    00
    00
    00
    00
    00
    00
    0A
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    44
    50
    31
    35
    39
    20
    20
    20
    01
    02
    39
    DP159_page1_v1_1.txt
    43
    01
    3F
    00
    A0
    00
    00
    00
    02
    00
    00
    33
    00
    00
    11
    00
    0F
    40
    00
    07
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    07
    70
    08
    00
    00
    00
    00
    00
    08
    01
    01
    08
    04
    06
    00
    00
    80
    80
    80
    80
    EE
    00
    00
    00
    F8
    03
    FF
    FF
    03
    20
    00
    70
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    40
    40
    40
    40
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    10
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    01
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    5E
    82
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    01
    
    DP159_page1_v2_1.txt
    43
    01
    3F
    00
    A0
    00
    00
    00
    02
    00
    00
    33
    00
    00
    11
    00
    0F
    40
    00
    07
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    07
    70
    08
    00
    00
    00
    00
    00
    08
    01
    01
    08
    04
    06
    00
    00
    80
    80
    80
    80
    C0
    00
    00
    00
    7F
    1F
    1F
    FF
    03
    20
    00
    70
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    40
    40
    40
    40
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    10
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    01
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    5E
    82
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    01
    

    To supplement the waveform through the oscilloscope OUT_CLK.

    Oscilloscope Stops running,and the distance between two adjacent troughs is about 6.7ns.(The period of 148.5MHz is 6.734ns.)

    Thank you for your patience.

    Regards.

  • 1. SDA_SNK and SCL_SNK pullup resistors need to be 2K for source application and 47k for sink application.

    2. Page 0 register is the I2C registers as listed in the DP159 datasheet. But the damp is not correct. Register 0x00h to 0x08h should show the DP159 DEVICE_ID and REV_ID which are READ only. Page 1 register shows the clock is detected but not locked.

    3. Are Channel 1 and Channel 2 the differential output of OUT_CLK? With Vsadj = 7.06k, you should see min of 400mV and max of 600mV single-ended output voltage swing. The current amplitude shows ~10mV.

    4. Any chance you can also measure the clock input?

    5. Does the FPGA indicate that it has locked to its own reference clock?

    Thanks

    David

  • Hi, David

    Based on your suggestion, I will adjust SDA_SNK and SCL_SNK pullup resistors.

    I reread page 0 register. The hex file as follows:

    DP159_page0_v4_1.txt
    44
    50
    31
    35
    39
    20
    20
    20
    01
    02
    39
    00
    00
    00
    00
    0F
    00
    00
    00
    00
    00
    80
    00
    F0
    00
    00
    00
    00
    01
    04
    40
    08
    0A
    

    The input clock of DP159 comes from the differential clock output by the FPGA, which comes from the single-ended clock signal output by the PLL.(PLL is locked)

    I measure the input clock , and the swing is also weak. The waveform displayed by the oscilloscope is as follows

    And I'm looking for a reason. 

    Thank you for your patient answer.

    Regards.

  • Hi, 

    First of all, I want to apologize.

    I made a wrong judgement because I did not set the appropriate input impedance of the oscilloscope terminal.

    The waveform after changing the input impedance of the oscilloscope is as follows:

    Waveform of DP159 Input Clock:

    Waveform of DP159 output Clock:

    sorry again.

    Regards.

  • The input clock of DP159 is corrent.

    The output voltage swing is too small to meet the requirement of minimum 400 mV and maximum 600 mV swing.

    Waveform of DP159 output Clock:

    The problem remains unsolved.

    Regards.

  • Can you please check your power up sequence? OE pin needs to be hold low when VCC/VDD ramps up and goes high after VCC/VDD are both stabilized.

    Can you also try to write a 0 to bit 0 of Page 1 Register 0x00h, and then write a 1 again to the same location? This would disable/enable the DP159 PLL.

    Have you checked the thermal pad of DP159 to see if it is properly connected to the board ground?

    Thanks

    David

  • Hi,

    1. I used a MCU pin to connect OE to reset DP159, and the reset time was long enough.

    2.  The thermal pad of DP159  is connected to the board ground.

    3. I try to reset DP159 PLL through write a 0 to bit 0 of Page 1 Register 0x00, and then write a 1 again to the same location .

    But the results have not improved.

    Waveform of DP159 output Clock:

    Regards.

  • Are you seeing this issue on multiple boards?

    Can you please provide a screen shot of VCC, VDD, and OE pin at the power-up?

    Thanks

    David

  • Hi, David

    I changed SDA_SINK and SCL_SNK from 3.3V to 5V, and the quality of OUT_CLK has been improved, except for the small swing.

    When I was debugging in one step, I tested OUT_CLK at OE = 0, and found that the output swing was several hundred millivolts, so I think that the small swing before was related to the size of the frequency.

    After I changed IN_CLK to 75MHz, the OUT_CLK swing meets the output requirements, and the single-ended output is about 500 mV.

    Whether the difference of OUT_CLK amplitude at different frequencies is related to impedance mismatch.

    (On my board, OUT_CLK and OUT_Dx of DP159 are connected directly to HDMI Receptacle)

    Thank you very much.

    Regards

  • Can you please dump out both Page 0 and Page 1 registers again with SCL_SNK and SDA_SNK being tied to 5V?

    When OE=0, the DP159 is in reset, the output clock is in High-Z state.

    The previous register dump shows the clock is being detected and the frequency is ~148.5MHz, but PLL is not locking for some reason.

    Please capture the power up timing of VCC, VDD, and OE pin.

    Can you also try to toggle HPD_SNK (low and then high) and see if output clock is ok?

    Thanks

    David

  • Hi,

    When I tested OUT_CLK, I found that the signal quality was not as good as yesterday's. It might be the oscilloscope settings.(Because of the circuit board design, the output signal is not easy to measure.)

     The value of  Page 0 and Page 1 registers when IN_CLK = 148.5MHz

    Page 0:

    DP159_page0_3_v1_1.txt
    44
    50
    31
    35
    39
    20
    20
    20
    01
    02
    39
    00
    00
    00
    00
    0F
    00
    00
    00
    00
    00
    80
    00
    10
    00
    00
    00
    00
    00
    00
    00
    00
    0A
    00
    

    Page 1:(The values read before and after are somewhat different.)

    DP159_page1_3_v1_1.txt
    C3
    01
    3F
    00
    A0
    00
    00
    00
    02
    00
    00
    33
    00
    00
    11
    00
    0F
    40
    00
    07
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    07
    70
    08
    00
    00
    00
    00
    00
    00
    00
    08
    08
    04
    06
    00
    00
    80
    80
    80
    80
    D6
    00
    00
    00
    FF
    80
    01
    FF
    03
    20
    00
    70
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    40
    40
    40
    40
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    10
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    11
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    5E
    82
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    01
    
    DP159_page1_3_v2_1.txt
    43
    01
    3F
    00
    A0
    00
    00
    00
    02
    00
    00
    33
    00
    00
    11
    00
    0F
    40
    00
    07
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    07
    70
    08
    00
    00
    00
    00
    00
    00
    00
    08
    08
    04
    06
    00
    00
    80
    80
    80
    80
    EC
    00
    00
    00
    FE
    FF
    03
    FF
    03
    20
    00
    70
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    40
    40
    40
    40
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    10
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    11
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    5E
    82
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    01
    

     The value of  Page 0 and Page 1 registers when IN_CLK = 75MHz

    Page 0 registers have the same value as above.

    Page 1:

    DP159_page1_3_v3_1.txt
    02
    00
    3F
    00
    A0
    00
    00
    00
    01
    00
    00
    33
    00
    00
    11
    00
    0F
    80
    00
    07
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    07
    B0
    0F
    00
    00
    00
    88
    08
    08
    08
    08
    08
    04
    06
    00
    00
    80
    80
    80
    80
    FF
    00
    00
    00
    FF
    FF
    FF
    FF
    03
    30
    77
    77
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    40
    40
    40
    40
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    10
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    11
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    2E
    82
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    01
    
    DP159_page1_3_v4_1.txt
    02
    00
    3F
    00
    A0
    00
    00
    00
    01
    00
    00
    33
    00
    00
    11
    00
    0F
    80
    00
    07
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    07
    B0
    0F
    00
    00
    00
    88
    08
    08
    08
    08
    08
    04
    06
    00
    00
    80
    80
    80
    80
    FF
    00
    00
    00
    FF
    FF
    FF
    FF
    03
    30
    77
    77
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    40
    40
    40
    40
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    10
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    11
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    2E
    82
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    00
    01
    

    I also try to toggle HPD_SNK, but OUT_CLK did not change significantly.

    As for the acquisition of VCC, VDD and OE timing, I will try it tomorrow. Because the oscilloscope I use has two channels, it needs a pair of tests.

    Thank you very much.

    Regards.

  • What is the difference between the version 2 and version 3 of the Page 1 register dump? Version 3 shows PLL is locked while version 2 shows PLL not locked, what has been changed between the two version?

    Thanks

    David

  • Hi,

    Under the same conditions, when reading the Page 1 register, I found that the value of the read register would be changed, and the value of the two read registers would be different.

    So, I dump out Page 1 register twice at the same input frequency, 

    DP159_page1_3_v1_1.txt  and DP159_page1_3_v2_1.txt is the result of two reads under the same condition and is read as IN_CLK = 148.5MHz.

    DP159_page1_3_v3_1.txt  and DP159_page1_3_v4_1.txt is the result of two reads under the same condition and is read as IN_CLK = 75MHz.

    The power up timing of VCC, VDD, and OE pin as following.

    Thank you very much.

    Regards.

  • Please refer to Figure 22 of the power-up timing requirement of DP159. In the scope capture, the OE pin is ramping up when VCC is starting to ramp up. The OE needs to go from low to high after VCC/VDD is stable with min of 100us. 

    Would you please change the OE pin so that it only has a pulldown capacitor? The pulldown capacitor and the internal pullup on OE pin will create a RC time constant delay. You need to change the capacitor on the OE pin so that the RC time constant delay meet the power-up timing requirement of Figure 22.

    Thanks

    David

  • Hi,

    When I first turned on, only the RC circuit worked (although an IO pin of the MCU connected OE), the grounding capacitance I used was 100nF (recommended 200nF), and the RC time T = RC = 200K * 100N = 0.02s.I think this time has met the requirements of the data manual.

    I changed a capacitor of 1uF, and OUT_CLK was not improved.

    Thank you very much.

    Regards.

  • Can you please provide a scope capture of VCC and OE pin? 

    The 1uF is too big as can be seen on the OE ramp up time. A 0.22uF cap should be sufficient as it will give you approximately 55ms ramping up time.

    Thanks
    David

  • Hi,

    I haven't found a capacitor of 0.22uF yet.

    The power up timing of VDD and OE pin as following.

    The power up timing of VCC and OE pin as following.

    Thank you.

    Regards.

  • I will wait until we finish the 0.22uF capacitor on the OE pin experiment. 

    1. We looked at the input clock and the input clock looks OK. 

    2. DP159 is able to detect the input clock and calculated clock frequency matches with the input clock frequency

    3. VCC power looks OK at 3.3V

    4. VDD power looks OK at 1.1V

    5. When you read the DP159 registers multiple times, the PLL lock bit does show being locked from time to time, so there is a system stability issue here

    5a. The system stability does not look like a I2C read issue because you can read DP159 device ID consistently

    5b The device may not be reset properly, this is the 0.22uF OE pin experiement

    5c Not enough thermal pad coverage on the DP159 so you don't have a good ground reference. 

    5d Possible cross-talk?

    Can I please take a look at your layout?

    Are you seeing the issue on multiple boards?

    Thanks

    David 

  • I changed the capacitance of OE pin to 0.22uF without any change. Here is the power-on sequence of OE, VCC and VDD.

    Thank you.

  • Can I please take a look at your layout?

    Thanks

    David

  • still need help?