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Linux/SN65DP159: DP159 EDID Read Wrong data

Part Number: SN65DP159

Tool/software: Linux

Hi Team
we use a SN65DP159RGZ at HDIM output, as show in figure. The input and output data of DP159 are both TMDS. We don't use the AUX function. Xilinx read the EDID of TV, Xilinx get wrong data sometimes. When we step over DP159, Xilinx connect  to TV directly, Xilinx always read right data. We suspect the I2c-over-AUX may effect EDID function. How can we close the I2c-over-AUX function?
Reading the registers of DP159 from I2C, we get registers values as follow:
   0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f                    0123456789abcdef
00: 44 50 31 35 39 20 20 20 01 02 38 00 00 00 00 0f    DP159   ??8....?
10: 00 00 00 00 00 00 00 50 00 00 00 00 00 00 00 00    .......P........
20: 8a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ?...............
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 00 00 00 00 00 000 00 00 00 00 00 00 00                 ................
why register 22h is 00 ?

  • Dajun

    Please leave AUX_SRCp/n floating, 

    For applications where the GPU or Sink does not support clock stretching the DDC lines from the GPU/DP TX should bypass the SCL_SRC and SDA_SRC but still connect to the SCL_SNK and SDA_SNK pins on the DP159. The SCL_SRC and SDA_SRC pins must be pulled to ground. Note that if the GPU/DP TX cannot support the 5V DDC lines from the connector, a level shifter is needed to step down the 5V signals to the voltage level the GPU/DP TX can support.

    Thanks

    David

  • We haven't  reserve pull-down resistor in PCB of SCL_SRC and SDA_SRC pins. Can SCL_SRC and SDA_SRC pins be floated?

  • Thank for your reply.The Xilinx's FAE told us that the IP core support clock stretch.So,are there any other suggestions? Thanks.

  • Dajun

    For some reason, the picture is missing in the original post so I can't see the connection anymore. Would you please share the connection diagram again?

    1. You can put the DP159 in the snoop mode. How to connect is in my previous post.

    2. Try to change the pullup resistors on the DDC and see if it makes any improvement.

    3. Try to run the I2C data rate at lower data rate.

    Thanks

    David

  • The diagarm is like this: The Network have a problem ,I can‘t upload picture.

    Xilinx --> DP159 --> connecter -->TV

    1. If we bypass DP159,buf we don't  reserve pull-down resistor in PCB of SCL_SRC and SDA_SRC pins , Can SCL_SRC and SDA_SRC pins be floated? 

    2.  We try to run the I2C data rate at lower data rate and it make some improvement.

    3. We have measured the SCL_SRC and SCL_SNK, we found the rate is different.The SCL_SNK is approximately 90KHz . SCL_SRC is sometimes 90KHz and sometimes 25KHz.Why the clock rate of SCL_SRC and SCL_SNK if different?

    Thanks

    Dajun

  • Dajun

    1. SCL_SRC and SDA_SRC must be pulled to GND. If left floating, noise could be coupled onto SCL_SRC and SDA_SRC and cause erroneous read of the DDC bus by the DP159.

    2. The DP159 implements I2C clock stretching on the SCL_SRC and SDA_SRC. It slows down communication by stretching the SCL_SRC signal. During an SCL low phase, any I2C device on the bus may additionally hold down SCL to prevent it from rising again, enabling it to slow down the SCL clock rate or to stop I2Ccommunication for a while. 

    3. I was looking to see the pullup resistor value on the DDC bus. You can try to change the pullup resistor value and see if it fixes the issue.

    Thanks

    David