SN75DP130: Power Sequence

user4999529

Prodigy 130 points

Part Number: SN75DP130

Hi Team

I read that "Vddd must be asserted first and stable for greater than 10 μs before Vcc is applied." from a datasheet.

However our prototype system is Vcc is first stable before Vddd is stable. (Reset sequence is ok.)

Is it OK? If bad, What will be happened to the device?

Thanks

Best regards,

Kawai

over 4 years ago

0 David (ASIC) Liu over 4 years ago

TI__Guru*** 139515 points

Kawai-san

There is no problem in Vdd-Vcc timing as long as reset is asserted. Reset should be asserted at least 100us after both Vcc and Vdd are stable.

Thanks

David

0 user4999529 over 4 years ago in reply to David (ASIC) Liu

Prodigy 130 points

Hi David

Thank you very much.

I have a related question.

The ramp time recommendation is less than 10ms from a datasheet.

However Vdd ramp time of our prototype system is about 38ms. (Please see attached .png; the blue wave is Vdd and the green one is RSTN)

Is it OK?

I think it is OK because RSTN will be once low after Vdd and Vcc are stable..... (To active SN75, RSTN will be controlled to high after attached .png wave.)

Thanks

Best regards,

Kawai

0 David (ASIC) Liu over 4 years ago in reply to user4999529

TI__Guru*** 139515 points

Kawai-san

This is fine, please make sure there is no operation until after the RSTn goes high again.

Thanks

David

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SN75DP130: Power Sequence