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SN65DP159: The issue of output clock frequency

Part Number: SN65DP159

Hello,

I would like to ask a question about issue on my project.

I am using SN65DP159RSBT on HDMI input interface.

After power-up, I set some registers to operate the device.

Then, 4K60p signal is input to this. But the output clock frequency of SN65DP159 is wrong.

- The input clock frequency is 148.5MHz.

- The output clock is frequency is approximately 37MHz.

After saw this issue, I changed the following register value.

After that, I measured that the output clock frequency is 148.5MHz same as input clock.

- Misc Control Register 0x0A b[2] : b0 -> b1

(Reference)

The setting of Misc Control Registers are below.

Except for 0x0A b[2] register, these registers have not changed after initialization.

0x09h  : 0x02

0x0Ah  : 0xB1

0x0Bh  : 0x1A

0x0Ch  : 0x00

0x0Dh  : 0x00

I'm not sure how to avoid this issue so far.

I would appreciate it if you could give me some advice for me.

  • Setting value of 0xB0h to register 0x0Ah forces DP159 into re-driver mode only. Re-driver will not work properly for 4K@60Hz, you need re-timer mode for 4K@60Hz, so the value of 0xB1h is correct.

    Please read register 0x0Bh the TMDS_CLOCK_RATIO_STATUS bit. For HDMI1.4, the TMDS_CLOCK_RATIO_STATUS bit is set to 0 while for HDMI2.0 (4K@60Hz) the TMDS_CLOCK_RATIO_STATUS bit is set to 1. 

    Thanks

    David

  • When input 4K60p signal after power-up, the TMDS_CLOCK_RATIO_STATUS bit is set to 1.

    But the output clock frequency is approximately 37MHz.

    Then, I wrote APPLY_RXTX_ CHANGES bit of register 0x0A to 1. After that, the clock frequency is 148.5MHz.

    When input 1080p 60Hz signal after power-up, the TMDS_CLOCK_RATIO_STATUS bit is set to 0.

    And the output clock frequency is 148.5MHz.

    This issue occurs when HDMI2.0 signal is input to SN65DP159 that is set retimer mode.

    So far I need to write APPLY_RXTX_CHANGES bit of register 0x0Ah to 1 to correct the output frequency.

    But I do not know the reason why SN65DP159 does not the output correct frequency when power-up.

  • 1. What is the default value of Register 0x0Ah, DEV_FUNC_MODE bit after power-up?

    2. When switching to HDMI2.0, does HPD_SNK get toggled?

    Thanks

    David

  • 1. After power-up, we set DEV_FUNC_MODE bit to b01 (default setting).

    2. We are using HPD snooping mode.

        After switching video signal from 1080p60Hz to HDMI2.0, SN65DP159 does not receive HPD pulse on HPD_SNK pin.

    Just in case, I tell you our issue again.

    For our issue, it occurs when HDMI2.0 signal input after power-up. 

       

  • Per the HDMI 2.0 spec, whenever the source changes the TMDS_BIT_CLOCK_RATIO bit from 0 to a 1, or from a 1 to a 0:

    • The source shall suspend the transmission of the TMDS clock and data.
    • Change the TMDS_BIT_CLOCK_Ration bit.
    • Allow min of 1ms and max of 10ms before resuming transmission of TMDS clock and data

    The problem here is the clock / data are already detected and running before the TMDS_CLOCK_RATIO bit gets set to enable 1/40 mode. In this case, the DP159 will try to adjust to a 1/40 ratio by slowing down the clock instead of keeping the clock rate the same and increasing the data rate. And this problem can be resolved by causing the receiver clock detect to restart (using HPD toggle, apply_rxtx_change, etc). 

    Thanks

    David

  • Thank you for sharing information.

    Eventually, I will write APPLY_RATX_CHANGES bit to correct the output clock.

    However, I would like to ask two questions about your comment.

     

    >Allow min of 1ms and max of 10ms before resuming transmission of TMDS clock and data

    Correctly, ” Allow min of 1ms and max of 100ms before resuming transmission of TMDS clock and data.”

    Is my recognition correct?

     

    >The problem here is the clock / data are already detected and running before the TMDS_CLOCK_RATIO bit gets set to enable 1/40 mode.

    >In this case, the DP159 will try to adjust to a 1/40 ratio by slowing the clock instead of keeping the clock the same and increasing the data rate.

     

    I understood what you explained but I have a question.

    In the DDC snooping mode, how long does SN65DP159 need to set TMDS_CLOCK_RATIO bit from snooping of SCDC command?

     

    Best regards,

  • Takeshi-san

    The max is 100ms, sorry for my typo.

    The min of 1ms is more than enough time for the DP159 to set the TMDS_CLOCK_RATIO bit from the DDC snoop.

    The issue here is that the source is non-HDMI compliant, and we have to toggle HPD_SNK, or the apply_rxtx_change bit to accommodate this condition.

    Thanks

    David