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TCAN4550-Q1: TX FIFO

Wayne Liu
Expert 8605 points
Part Number: TCAN4550-Q1

Hi

Could you please help to reply below questions?

The process is: 10 TX FIFO, period is 10ms, inquire FIFO TX status(TXFQS), send packages in the idle(empty) FIFO(Copy 5 packages, send them by TXBAR), wait for the next 10ms. 

After inquiring FIFO status and setting  break point, we found idle FIFO is more than 10,  but if we inquire FIFO then set break point, then send and set break point again, wait for a little bit longer, then inquire FIFO again, the idle FIFO is 10. 

I think there should be 10 idle FIFO after inquiring and setting break point, because 10ms is enough for sending 5 packages, but I need to wait for longer to ensure there are 10 idle FIFO. 

Is this normal? If the FIFO will be refreshed to empty after sending packages? 

Thanks.  

  • 0
    TI__Guru 60262 points

    Wayne,

    One thing to note is that the FIFO free level in TXFQS register doesn't update until FIFO messages are transmitted using TXBAR. So if you write messages to it and then set a break point, then read the free level, it will still read as empty until those messages are transmitted. That being said, I'm not quite sure why you're seeing the more than 10 idle FIFO when you're configuring for 10 FIFO.

    Can you give the value of the TXBC register (0x10C0)? The memory configuration might be throwing something off, it sounds like more than 10 TX FIFO are being configured, then once you send some messages, the free level is updated to 10 idle FIFO. Your FIFO should be refreshed to empty after sending packages though, they can be overwritten though.

    Regards,

  • 0 in reply to Eric Hackett
    TI__Guru 62910 points

    Hi Wayne,

    Do you have any updates to share on this?  Have you had a chance to review Eric's comments above?

    Regards,
    Max

  • 0 in reply to Max Robertson
    TI__Expert 8605 points

    Thanks Max and Eric.

    I have told customer how to do it, they are taking summer holidays now, so no feedback at the moment, I think we have closed the case. 

  • 0 in reply to Wayne Liu
    TI__Expert 8605 points

    Max, Eric,

    Customer went back to work and told me that the issue is not closed yet. 

    Let me clarify the issue again, 

    if they use below commands: 1. read fifo status, 2. copy and send, send request, 3. wait for the next 10ms(no other operation, just wait), 4. read the fifo status, there are always 10 empty fifo, this is normal. 

    if they use below commands: 1. read fifo status, 2. copy and send, send request, 3. wait for the next 10ms(During this 10ms, they send 5 frames, but it is completed in 8ms), 4. read the fifo status, sometimes there are 10 empty fifo, but sometimes it is less than 10. This is abnormal. This is my issue. 

    The TXBC is: TFQM=0, TFQS[5:0]=10, NDTB[5:0]=0, TBSA[15:0] is automatically calculated. 

  • 0 in reply to Wayne Liu
    TI__Guru 60262 points

    Wayne,

    Thank you for the clarification and follow-up. 

    Just to make sure I understand:

    In both cases, the TXFIFO status is read from TXFQS, then messages are place in the TXFIFO and a send request is executed, 10ms wait, and then read the TXFQS register again. The only difference is that in the second case 5 frames are transmitted during the wait period. I guess I'm a little confused at why frames in the first case aren't set if the TXBAR is written to for those messages.

    This could be a case where sometimes the messages are sent correctly, so the TXFIFO is completely emptied after the copy and send request. Then in the case where there are less than 10 empty TXFIFO, some of the messages weren't transmitted correctly, and are still occupying space in the FIFO.

    Is there any way the CCCR register can be read (0x1018)? As well as the TXBPR register (0x10CC) and the interrupt register (0x1050) after the case where the TXFIFO doesn't show the right number?

    Regards,

  • 0 in reply to Eric Hackett
    TI__Expert 8605 points

    Eric,

    This issue is closed now. Their timer for the 10ms is not fixed during the 10ms, so sometimes there is less than 10ms then the packages are all not sent, so the empty FIFO is less than 10 sometimes.

    Thanks for your support.