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DS100DF410: DS100DF410 cannot pass the PRBS9 test

Part Number: DS100DF410

Hi team,

My customer is using the device DS100DF410 now. But cannot pass the PRBS9 test although we have bypass the CDR. Do you have some ideas how to improve it? Thanks.

  • Hi Frank,

    Is this the same case as the one we are corresponding with via direct email? As per my previous message the customer should make sure to put the retimer in CDR reset while configuring the channel registers for EQ settings, and then release the CDR reset when configuration is completed.

    Unfortunately when the CDR is not locked the retimer EOM function does not work. However if the customer downstream ASIC SerDes has eye measurement capability, then you may sweep both retimer CTLE boost settings and Tx VOD and de-emphasis and use the settings that yield the best eye opening at the ASIC input.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • Hi Rodrigo,

    Not the same case, whether we have some experience about the device can pass PRBS9? Thanks.

  • Hi Rodrigo,

    Thanks. currently the customer has followed our guideline, still meet the problem. I am not sure whether the device can be used for PRBS9. Do we have some experience?  We still cannot find the reason. Feel free to share your ideas. Thanks.    

    {0xff, 0x04},    // change channel

    {0x00, 0x04},  //reset channel register

    {0x0a, 0x5c},  // reset CDR

    ……

    {0x09, 0x20}, //bypass CDR

                      ……

    {0x0a, 0x50}  // release CDR

    Regards

  • Hi team,

    Whether we can use the internal PRBS9 generator to check it? First i want to make sure we can support PRBS9. Thanks.

  • Hi Frank,

    First off I can assure you that there is no interoperability issue with the TI retimer and PRBS9 pattern. We have used this test pattern extensively on multiple validation tests.

    The customer's routine for enabling CDR bypass is incomplete. See below corrected routine with the missing write operations.

    0xff, 0x04},    // change channel

    {0x00, 0x04},  //reset channel register

    {0x0a, 0x5c},  // reset CDR

    {0x09, 0x20}, // PFD override enable

    {0x1E, 0x01}, //Enable CDR bypass raw data mode

    {0x3F, 0x80}, // disable the fast cap re-search

    {0x0a, 0x50}  // release CDR reset

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer