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TL16C752D: Receive Timing in FIFO mode

Part Number: TL16C752D

Hello,

The following phenomenon has occurred in my customer.

RXRDY goes High before IOR goes High in Receive Timing in FIFO mode.
It looks different from D / S Figure 6, why? Is this correct behavior?

I'm aware of this phenomenon as follows. Is my understanding correct?
・ IOR Storb width is Characterized only for the minimum value
・ The condition that RXRDY goes High is when FIFO becomes Empty.
・ Even if Low is input to IOR, RXRDY goes High if the Storb width spec is satisfied and the FIFO is empty.
So, I think that is normal behavior.

Is my understanding correct?
Please leave a comment.

Best Regards,

Kaede Kudo

  • Hey Kaede,

    "RXRDY goes High before IOR goes High in Receive Timing in FIFO mode.
    It looks different from D / S Figure 6, why? Is this correct behavior?"

    Do you have a scopeshot of this?

    "The condition that RXRDY goes High is when FIFO becomes Empty."

    The other condition which is mentioned in the datasheet is if some kind of RX FIFO error occured. The errors are discussed in the LSR section of the datasheet (bit 7) in section 8.5.6 page 33.

    Otherways I could imagine the RXRDY pin going high is if you

    1) reset the device (Table 3 shows the pin going high after reset)

    2) cleared the RX FIFO register (setting FCR bit 1)

    Thanks,

    -Bobby

  • Hello Bobby,

    Thank you for your reply.

    - Do you have a scopeshot of this?

    Yes, Paste the scopeshot I have deployed from the customer below.

    This is a cut-out of the relevant part from the customer's materials.
    Please comment if missing Information.

    - About RXRDY pin going High

    I recognized that the conditions for the RXRDY pin to go High are as follows.

    *RX FIFO is empty
    *There is an error in RX FIFO
    *reset the device
    *cleared the RX FIFO register

    When the above conditions are met, can the TL16C752D be considered to set RXRDY High even when IOR is Low?

    Best Regards, 
    Kaede Kudo

  • Hey Kaede,

    Thanks for the additional information.

    "When the above conditions are met, can the TL16C752D be considered to set RXRDY High even when IOR is Low?"

    This sounds correct to me. If the timescale is 10ns/div then we can say that the IOR was likely strobed and the last byte of data was read. Then the RXRDY pin goes HIGH.

    The user is not seeing any errors in their communication correct?

    Thanks,

    -Bobby

  • Hey Bobby,

    Thanks for your comment.

    I understood that my perception was not wrong.

    I would like to contact the customer with the following:

    Even if the IOR pin is low, the RXRDY pin may go high first.
    ・ When the last byte of data was read.
    ・ When any errors occurs in their communication
    Are the above conditions true?

    Best Regards,

    Kaede Kudo

  • Hey Kaede,

    Sorry for the late reply on this one. RXRDY should go high when the RX FIFO is empty. It shouldn't go high because an error occurs in communication. I believe that is captured through the INT pin and inside of our IIR.

    Thanks,

    -Bobby