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DS90UH947-Q1: I2c multi-master 'undefined behaviour'

Johann Johann
Prodigy 100 points
Part Number: DS90UH947-Q1

Hi everyone,

i have a question regarding section 7.5.3 'I2C Restrictions on Multi-Master Operation' on page 36.

The I2C specification does not provide for arbitration between masters under certain conditions.
The system should make sure the following conditions cannot occur to prevent undefined conditions on
the I2C bus:

  • Master 1 sends a repeated START condition and master 2 sends a data    bit.
  • Master 1 sends a STOP condition and master 2 sends a data bit.
  • Master 1 sends a repeated START condition and master 2 sends a STOP

Note that these restrictions mainly apply to accessing the same register offsets within a specific I2C slave

If this a limitation of I2C at its core, how can this be solved for newer generations of as indicated in 7.5.4?
It states that these restrictions mainly apply to accesses to the same device and register.
What other conditions are there?

  • 0
    TI__Mastermind 31590 points

    Hi Johann,

    In the statement section 7.5.4, the newer devices have the I2C implementation of the arbitration where all the commands are in the queued. The high priority will execute first whereas least priority will be executed in later in order of the queue.

    Aaron

  • 0 in reply to Aaron Heng
    Prodigy 100 points

    So the statement in 7.5.4 doesn't relate to the general problem of I2C itself that is mentioned in 7.5.3 ?
    Can you provide a link to more information about the 'undefined behaviour' in 7.5.3 and the implications of this?

    Thank you

  • 0 in reply to Johann Johann
    TI__Mastermind 31590 points

    Hi Johann,

    I'm sorry for the delayed response. I created two slides, and hope this help clarify your answer. Basically it’s up to the user to implement a mechanism to handle their multi-master scenarios for 94x. The 94x suggests utilizing mailbox registers to address multiple transactions and arbitration based on the prioritization scheme.

    Assuming the deserializer has the mailbox0 (SPARE0) and mailbox1 (SPARE1), the mailbox is available in order to prevent two masters accessing to the deserilaizer at the same time. Let's say if the SoC wants to access to the deserializer registers, it must check the mailbox registers (for example 0x18 and 0x19) if the local MCU access to the registers. If mailbox register is 0xFF value then the local MCU is currently accessing to the register. It is very similar scenarios when local MCU wants to access to the registers

    Hope this helps. Let me know if you have any other questions.

    Mailbox_Mechanism.pdf

    Aaron