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TL16C752D: Reading IIR Register timing and INT generate timing

KAEDE KUDO
Expert 2700 points
Part Number: TL16C752D

Hello, 

My customer has a question about IIR.
They are reading IIR before INT becomes Active.

[Q1]
Is it possible that IIR = 0x03h?

IIR bit0 = 1 is No interrupt is pending.
At this time, IIR bit [3: 1] value is Don't care.
Therefore, I think that there is no problem with the above values.

Q2
What happens if the IIR Read and interrupt generate timing conflict?

Q3
Is there an errata in the collision between IIR read and interrupt generate?

Best Regards,

Kaede Kudo

  • 0
    TI__Mastermind 49110 points

    Hey Kaede,

    Q1:

    I haven't done any active scans of the IIR when I've used the device prior so I am actually unsure of the answer. If you have a register initialization and test sequence for me to run to verify this, I can try to see if I can reproduce something that would create it otherwise I'm unsure.

    My best guess is that if bit 0 is 1, there should be no interrupts to read. Table 15 in the datasheet seems to state bit 0 is expected to be 0 in those interrupts sources.

    Q2:

    Can you show me an example? I'm not sure I follow? Are you saying there is an interrupt but it does not show up in the IIR?

    Q3:

    There are no erratas out for the TL16C752D device.

    -Bobby

  • 0 in reply to BOBBY
    Expert 2700 points

    Hello Bobby,

    Thank you for your reply.

    I will contact you because I have a clearer background and requirements from the customer.
    Can you check it?
    They are in a very rushing situation, so it would be helpful to answer early.

    [background]
    After completing Tx, confirm that INT pin is High, and perform IIR Read.
    Perform processing corresponding to Interrupt Source indicated by IIR, and then read IIR.
    The value of IIR at this time is 0x03h.
    * The second IIR Read does not mean to read when the INT Pin rises.
    　As for Timing, IIR Read is performed at the timing when TXRDY falls to Low.
    * The purpose of reading the IIR for the second time is to check if any other interrupt has occurred.

    [Customer views on 0x03h]
    IIR is read after the completion of the first interrupt processing.
    The timing when the contents of IIR change and the timing of Read are batting.
    So, can I read the value of bit0 = 1 indicating completion of interrupt reset and bit [3: 1] ≠ 000 indicating the second interrupt source?

    [Question]
    1． Can the value of 0x03h be read when IIR is read under the same conditions?
    * Is it possible to read IIR when TXRDY falls after interrupt processing?

    - initial setting
    LCR=0x03
    *Word Length=8bits
    *1 stop bits
    *No Parity
    *Normal Opeartion Condition
    *Break Control Bit=Noraml Opeartion Condition

    Set EFR=0x00
    *No Transmit flow control
    *No Receiver flow control
    *Enhanced function Disabled
    *Normal Operation
    *RTS Flow Control Disable
    *CTS Flow Control Disable

    Set FCR=0x0F
    *Enable the transmit and receive FIFOs
    *Clears the receive FIFO and resets its counter logic to 0
    *Clears the transmit FIFO and resets its counter logic to 0.
    *DMA mode=1
    *Sets the trigger level for the RX FIFO:1 characters
    *Sets the trigger level for the TX FIFO:8 spaces

    Set IER=0x0F
    *Enable the RHR interrupt
    *Enable the receiver line status interrupt
    *Enable the THR interrupt
    *Enable the modem status register interrupt

    2. When the opinion about 0x03h is not wrong, is it safe to determine that the value of IIR bit [3: 1] is the interrupt source that is currently occurring and execute the process?
    * Is the value of bit0 of IIR read at the above timing ignorable?

    3． Are there any procedures and conditions recommended by TI regarding the behavior and processing of the INT pin when multiple interrupts are generated?

    Example: When THR and RHR interrupts occur simultaneously, reading IIR at the rising edge of INT should indicate RHR Interrupt.
    When can I confirm that a THR interrupt has occurred after performing RHR Interrupt RESET processing?
    ・ After INT goes low, will it go high again before reading IIR?
    ・ Is INT always High and is it necessary to set up a delay after processing and read IIR again?
    I don't know the behavior of INT when multiple interrupts are generated, the reset processing and the reflection timing to the IIR register.

    Best Regards,

    Kaede Kudo

  • 0 in reply to KAEDE KUDO
    Expert 2700 points

    Hello Bobby,


    Could you tell us how the INT pin and IIR behave when multiple interrupts occur?

    Best Regards,

    Kaede Kudo

  • 0 in reply to KAEDE KUDO
    TI__Mastermind 49110 points

    Hey Kaede,

    Sorry for the delay in response, we had a national holiday on Monday (the day you sent the detailed post) and I was not in the office yesterday.

    --------------------

    "So, can I read the value of bit0 = 1 indicating completion of interrupt reset and bit [3: 1] ≠ 000 indicating the second interrupt source?"

    Just to double check here, the customer has confirmed that they see 0x03h?

    "2. When the opinion about 0x03h is not wrong, is it safe to determine that the value of IIR bit [3: 1] is the interrupt source that is currently occurring and execute the process?
    * Is the value of bit0 of IIR read at the above timing ignorable?"

    There is a priority level to the interrupts, if there are multiple interrupts then you can see the one with the highest priority when you read IIR. If you see that IIR bit 3:1 are non-zero, you should initiate your interrupt service routine. (bit 0 would make no sense to read in this case).

    "Example: When THR and RHR interrupts occur simultaneously, reading IIR at the rising edge of INT should indicate RHR Interrupt.

    An alternative approach is to look at the TXRDY and RXRDY pins of the device to see if there is data (you can set DMA mode 0 for them to trigger at 1 byte). TXRDY goes low when the FIFO is empty and RXRDY goes low when there is atleast one byte in the RX FIFO.

    Another approach (I've used this approach the most when using this device) is to use the LSR register and read bit5 to see if THR is empty or bit 0 to see if RHR has values stored in the FIFO.
    When can I confirm that a THR interrupt has occurred after performing RHR Interrupt RESET processing?
    ・ After INT goes low, will it go high again before reading IIR?
    ・ Is INT always High and is it necessary to set up a delay after processing and read IIR again?

    It should remain high if you have multiple interrupts
    I don't know the behavior of INT when multiple interrupts are generated, the reset processing and the reflection timing to the IIR register."

    If there are multiple INTs then the INT with the highest priority will show up in the IIR. (the other INTs should still be there unless you addressed them earlier). You can see the priority level on the far left column of Table 15.

    -Bobby

  • 0 in reply to BOBBY
    Expert 2700 points

    Hey Bobby,

    Thank you for your reply!
    I'm sorry to hurry without knowing it is a vacation.

    They say they read 0x03h.
    And I'm confused because it's not on the IIR Priolity list.

    However, if I tell them that there is no problem masking bit0 and that I can read the RDY pin and LSR to check the Interrupt, I think this will be closed.

    Tell them your answers and come back again.
    I believe you can close this thanks to your answers.

    Best Regards,

    Kaede Kudo

  • 0 in reply to KAEDE KUDO
    Expert 2700 points

    Hey Bobby, 

    When they read IIR = 0x03, they seem to take measures by ignoring bit0.

    I appreciate your cooperation!

    Thank you.

    Best Regards,

    Kaede Kudo