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TLK110 MDIO communication trouble
Part Number: TLK110
We are experiencing the same issue as described in
The problem appears to occur in batches of boards, and seems to occur most reliably in the temperature range 38 to 48C. We are powering from a single 3V3 supply which has a rise time of ~100us, and the reset signal to the PHY is asserted for >80ms after the 3V3 is stable.
We can't see any significant differences on the PHY pins in the cases where the device does not reset correctly.
Can you detail how the issue was resolved with your earlier customer please.
1. Do you see RX_CLK coming out ?
2. Is Clock available to PHY before the Power is applied ?
3. Have you tried ramping the 3V3 faster ?
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In reply to Geet Modi:
In answer to your questions :
1. When the TLK resets successfully we see RX_CLK coming out as soon as CLK on X1 is applied, on failure the RX_CLK sits at about 1.3V.
2. Our CLK to the TLK (on X1) comes from an FPGA and sits at 0V until the FPGA has been configured; the CLK starts about 1.25 Seconds after the 3V3 is applied.
We attempted applying an extra reset pulse after the clock had started in the case where the TLK had not reset, but this did not make any difference in that the TLK did not start after the reset was removed.
3. Unfortunately we can't ramp the 3V3 any faster than the present 100us because of consideration of maximum supply ramp rates to other parts on the same supply.
In reply to Bob Grice:
Thanks for the details.
On step 2, if you provide clock before Power Supply is ramped as specified in datasheet, do you still see the issue ?
I am closing this thread. In case you need further assistance, please open new thread and provide reference to this thread.
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