Part Number: DS90UB926QSEVB
Function Description:In the figure above, video equipment is a video output device and display equipment is a video receiving device. Now we need to make a device to collect video data between video and display. According to this function, figure 1 and Figure 2 in the figure above are designed. The main functions of the two schemes are as follows:Receive a fpdlink III signal, assign this signal to an external port, and collect the received fpdlink III signal into FPGA. FPGA needs to complete the data conversion from RGB to YUV422, and then convert the YUV422 data to Mipi csi2 signal output through a chip.
According to the function, there are two schemes, figure 1 and Figure 2. But now there are several problems as follows:1. Using Figure 1 scheme, please recommend which model of Ti chip meets some functions of "which chip". (this scheme is preferred)2. Figrue2 scheme is adopted, and 926 and 925 are configured as repeater mode. How to configure I2C registers of these two chips Since the whole video has been transmitted through 926 and 925, the transmission process is 925 - > 926 - > 925 - > 926. The whole design purpose is to collect data transparently. What's a good processing method for I2C?
Figure 2 is much more feasible for the function you are trying to achieve. The I2C can be set up to pass through the first 926 using the "slave address" and "slave alias" registers. That way the middle point looks transparent to the source. See registers 0x08-0x17 for configuration of slave addresses and aliases. You can also take a look at this app note on I2C addressing for FPD-Link. The same concepts here apply for 926/925: http://www.ti.com/lit/an/snla222/snla222.pdf
What is the PCLK rate for this system? One thing you will need to be extra careful about is the high speed connections for the RGB fanout from 926. You must take extra care to ensure stubs are minimized on the RGB pin outputs going to two sink devices, otherwise the SI may be degraded.
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In reply to Casey McCrea:
The transmission process is A( 925) - >B( 926) - >C( 925) - >D( 926). Which chip is selected to configure the "slave address" and "slave alias" registers? A or B or C or D ?
In reply to user313175:
The resolution of pixel is 1280 x 1024 and the frame rate is 60 HZ。
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