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Part Number: DS110DF410
At room temperature, after successful chain construction, the signal is cooled down to low temperature. When the signal reaches -25℃, CRC and port down/up will appear on corresponding ports.
Structure: MAC<- >Re-timer<- > Port
In case of problems, by reading 0x27 and 0x28 , it is found that the eye height and eye width of the signal received by re-timer become small... However, when something goes wrong, the CDR of the corresponding port will be reset and can be back to normal.
1. What cause this effect, is there a temperature limit?
2. From which register that I could read the current status of CTLE?
1). It may be because due to the temperature change CTlE settings may not be optimum. If you reset CDR at -25DegC does device recover?
2). You can read register 0x03 to read CTLE settings.
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In reply to Nasser Mohammadi:
Thanks for your reply.
1.The device could recover if I reset at -25 degree.
2.I have read the 0X03 that the value is both 0x0 for normal and abnormal operation.
Is there any way that I could optimize and keep the CTLE setting ? Thanks.
In reply to Tess Chen:
Table: Enable the DFE, adapt mode 2
SHARED/CHANNEL REGISTER SET
REGISTER ADDRESS [HEX]
REGISTER VALUE [HEX]
WRITE MASK [HEX]
Enable DFE (DFE_PD=0)Adapt Mode = 2
In reply to Rodrigo Natal:
1. The value 0x03 when initializing the re-timer room temp vs -25C are always 0x0.
2. We have tried the DFE enable in mode 1/2/3, this cannot help with our issue.
1. Do you have any other suggestion for to solve this issue?
2. We tried to manually set the CTLE, as the procedure below:
To manually override the CTLE boost under all conditions, perform the following steps.
1. Set the DS110DF410 channel adapt mode to 0 by writing 0x0 to bits 6:5 of channel register 0x31.
2. Set the desired CTLE boost setting in register 0x3a. If the DS110DF410 loses lock and attempts to lock to a lower data rate, it will use this CTLE boost setting.
3. Set the desired CTLE boost setting in register 0x03.
4. Set the desired CTLE boost setting in register 0x40.
5. If desired, set the CTLE stage 3 limiting bit, bit 2 of register 0x13.
a. The manually CTLE could only work with mode 0? what's the procedure for mode 1/2/3 ?
b. Why just set the 0x40 rather than 0x40-ox5f (table 11 in datasheet)?
c. When have the CTLE adaption Table 11 have the index from 0x40-0x5F, how does the adaption works? The value can be any value from the table 11, or it just give the range of adaption?
Thanks for your help.
Your reported test results seem contradictory.
HSSC Applications Engineer
-The value of 0x03 really no change and is 0x03 even wen the eye become small
- The surface temperature of re-timer for the -25C tmp is about -5 to -7 degree.
I've responded to you via direct email.
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