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DP83867CS: SGMII 4 wire interface

Part Number: DP83867CS

Hi all

Would you mind if we ask DP83867CS?

<Condition>
MAC IF : SGMII 4-Wire Connections
PHY : 25MHz(For example)
CPU : 200MHz(For example)

In case of SGMII 4-Wire connections, do PHY's clock and CPU's clock require to synchronize?
We assume that PHY's clock and CPU's clock don't require to synchronize.

Kind regards,

Hirotaka Matsumoto

  • Hello Hirotaka-san,

    Please refer to "8.4.1.1 Serial GMII (SGMII)" of the datasheet.The MACs capability effects how SGMII needs to be configured 4-wire vs 6-wire.

    "Clock and data recovery are performed in the MAC and in the PHY, so no additional differential pair is required for clocking. Alternately, if the MAC is not capable of recovering the clock from the SGMII receive data, the DP83867 can be configured to provide the SGMII receive clock through a differential pair."

    Thanks,

    Vibhu

  • Vibhu san

    Thank you for your reply!

    As the background of this question, the customer uses DP83867CS with follow condtions;

    <Conditions>
    MAC IF : SGMII 4-Wire Connections
    PHY : 25MHz
    CPU : 200MHz

    In case of these conditions without unsyncronized the clock between FPGA's one and PHY's one, it couldn't link up.
    So, we assume that it depends on the MAC setting.
    Should we confirm register SGMII_ANEG_STS(Address=0x0037)?

    Kind regards,

    Hirotaka Matsumoto

  • Vibhu san

    We could solve it. There is the problem of wiring length at differential pairs.

    Kind regards,

    Hirotaka Matsumoto



  • Hello Hirotaka-san,

    Good to hear!

    Thanks,

    Vibhu