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SN65DSI86: Skew question

Jeff Coletti
Expert 8645 points
Part Number: SN65DSI86

Hi team

Need some help with this, here is the customers question, this is a USBC application

We are using TI’s SN65DSI86 MIPI DSI to eDP bridge IC. As I work through the physical layout of the USB superspeed pairs, I am struggling to determine the exact length matching requirements for the display port auxiliary mode. I am hoping you can help.

 

At the moment, I have inter-lane USB pairs matched to <5mils (TX1P/TX1N). It is my understanding that the display port mode uses TX1 and RX1 together as video output and must be synced together. I am wondering if your chip has the ability to adjust for minor propagation delay variation between TX1/RX1 and TX2/RX2. If so, how much variation can it adjust for? What is the overall length matching/delay requirement to avoid issues?

Thanks

Jeff Coletti

  • 0
    TI__Guru*** 139515 points

    Jeff

    The DP spec allows for up to 1250ps of lane to lane (inter-pair) skew.  This is spec'ed at the DP connector. There will be some skew going through the Type-C MUX and it will be part of the 1250ps skew budget. I would recommend keeping the skew to within 25mil.

    For intra-pair skews, I would recommend keep it to less than 5mils.

    Thanks

    David