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DS90UH941AS-Q1: M/N divider questions

Part Number: DS90UH941AS-Q1

Experts,

I want to confirm :

1. Pclk can be configured as Fdsi*Ndsi_lanes*M/(12*N) in DSI reference clock mode, right?

2. Pclk can be configured as REFCLK0*M/N in External Reference Clock Mode, right?