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DS90UH941AS-Q1: M/N divider questions

Prodigy 290 points

Replies: 7

Views: 167

Part Number: DS90UH941AS-Q1

Experts,

I want to confirm :

1. Pclk can be configured as Fdsi*Ndsi_lanes*M/(12*N) in DSI reference clock mode, right?

2. Pclk can be configured as REFCLK0*M/N in External Reference Clock Mode, right?

  • Hello Ryan,

    Technically yes, number 1 is possible and number 2 is possible in splitter mode. However there is some complication here because when the DSI bit clock and the FPD III bit clock do not match, the device will add and remove some horizontal blanking in order to keep the video FIFO from overflowing or under-running. This is a complicated topic which we will generate an app note about in the future. For the time-being if you could give us some specifics on what clock rates you are trying to achieve we can test the situation and provide feedback. 

    Best Regards,

    Casey 

  • In reply to Casey McCrea:

    Casey,

    thanks for quick feedback during Christmas holiday.

    I will feedback you DSI clk and Pclk after customer make decision.

    For external reference clock  mode, they want to choose external clock 125MHz, Pclk 100MHz for splitter mode, is it OK?

  • In reply to Ryan Wang:

    Ryan,

    if you can make sure that the PCLK freq. is 100MHz, you can select the external PCLK as 100MHz as well, and the freq. accuracy is <+/-50PPM.

    best regards,

    Steven

  • In reply to Junqiang Shi:

    Ryan,

    What do you mean by 100MHz splitter mode? Is the customer planning to drive two separate displays? Can you provide a block diagram with resolutions and PCLKs? 

    Thanks,

    Casey 

  • In reply to Casey McCrea:

    Casey, Steven,

    thanks for your feedback. Attached is whole block and parameter. Could you help to check whether it is OK.DS90uh941-948block.pptx

    DS90uh941-948block.pptx

  • In reply to Ryan Wang:

    Hello Ryan,

    This configuration is ok assuming they are using 4 DSI lanes. For PCLK from DSI clock mode the formula for PCLK is found in datasheet section 8.4.2.2.1

    So 300MHz is correct for the DSI clock. For the external REFCLK I would suggest choosing 100MHz for the oscillator to avoid complication with M/N dividers. Since the M/N value is non-integer, it will introduce more jitter into the FPD-Link channel so 100MHz oscillator would be better. 

    Also for future reference, what is shown in your diagram is called "Dual FPD-Link" mode, not "Splitter" mode. Splitter mode is used for splitting one superframe image to two different displays. 

    Best Regards,

    Casey 

  • In reply to Casey McCrea:

    Casey,

    Thanks a lot for your help

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