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DS90UB941AS-Q1: Eye diagram configuration

Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: ALP

Hello,

I am performing an eye diagram analysis on a SerDes link (941 <=> 948).

We already made some eye diagram with the 949 <=> 948 and it worked fine using the following:

CDR loop BW = Fpclk / 40

High pass filter order 2, Freq = Fpclk / 40

If i use the same configuration, the eye analysis is definitively NOK

If, i change the DSI CLOCK MODE to : Register (0x56 : BRIDGE_CLK_MODE = DSI Burst mode with internal ref), then it is ok:

Is there a specific CDR configuration for the 941 / 948 SerDes link ?

According to the 941 datasheet, the CDR BW is F/15 , but F is not clearly defined

Is there more jitter with the DSI PCLK in general ?

Thanks,

Best regards

Alex

  • Hello Alex,

    What is your intended mode of usage for 941AS? PCLK from DSI clock mode? 

    Best Regards,

    Casey 

  • Hello Casey,

    Yes, we are currently using the DSI ref clock : Register (0x56 : BRIDGE_CLK_MODE = DSI non Burst mode the FPD Link is synchronous to the DSI Clock)

    Best regards,

    Alexandre

  • Hello Alex,

    What is the DSI clock frequency and when you are running in this mode are you getting a solid lock to the 948 partner device?

    Best Regards,

    Casey 

  • Hello Casey,

    I am in a configuration with short cable and small attenuation (-7dB at 3 GHz) and i don't need to activate the LINK ERROR COUNT (0x41) on 948

    The lock status is "solid" (no event on trig with my scope).

    Alex

  • Alex, 

    Thanks but what is the DIS clock frequency being provided to the 941AS and can you confirm that the DSI input clock is in continuous mode?

    Best Regards,
    Casey 

  • Casey,

    DSI frequency is 215MHz in continuous mode.

    Is there a different procedure and configuration for the eye analysis compared to a 948 - 949 configuration ?

    Alex

  • Hello Alex,

    Thanks for the detail. Ok so 215MHz DSI should set PCLK = ~72MHz assuming 4 lane DSI. For the scope setup please use CDR BW = f/15 where f = 72MHz and do not apply any additional filters. Also is this being measured at CMLOUT of the 948? It would be good to confirm the operating mode for 948 (dual link or single link) as that will change the expected frequency of the output pattern from 1.26GHz in single link mode to 630MHz in dual link mode. 

    Best Regards,

    Casey 

  • Casey,

    It look like the beginning of my questions (Loop BW of CDR = 4.8MHz, no filter)

    Regarding CMLOUT, yes, i am using it on 948 eval board

    We are in a single link, coaxial.

    The DSI lane number is indeed 4

    What is the recommended record length for your eye analysis ? 400us ?

    Alexandre

  • Alex,

    Based on the above it seems that your scope setup is correct. I think the large difference you are seeing between this and the scope shot using internal REFCLK is that the internal clock is running much slower in your test. Your somewhat closed eye is running at ~1.26GHz while the open eye is running at ~800MHz. 

    Additionally it should be noted that CMLOUT is not 100% accurate as a representation of the real signal quality at the 948 input, especially running at higher speeds. I would suggest trying the margin analysis program within ALP to check the link margin instead of CMLOUT here: https://www.ti.com/lit/ug/snlu243/snlu243.pdf

    Also you could look at the real signal input to the 948 by disconnecting the cable and running the 941AS output directly into a scope after the cable. To do this you would force "link ready" and force single FPD-Link mode in the registers for 941AS. This will allow you to look at the forward channel eye after the cable without the back channel or all the internal CMLOUT circuitry of the 948. 

    Best Regards,

    Casey 

  • Casey,

    Thanks for all your great support :)

    The results of the eye analysis on the FPD Link directly, and your registers recommandations doesn't change the eye opening.

    We already realize the margin analysis, with the attenuation measurement of the cable link

    Below the results with one simple cable for our prototypes

    Below the results with our final configuration.

    What is the recommended maximum attenuation at 1,3 GHz ?

    What is the best method to measure the quality of the FPD Link ?

    We initiate the measurement of the eye because of the screen flickering, and the bad margin analysis in our final configuration.

    Best regards,

    Alexandre

  • Hell Alex,

    The insertion loss is definatily higher on the second prototype and that may be a contributing factor to the performance but the actual loss isn't too excessive. I would recommend keeping IL < ~10dB at 1.3GHz. However I think the larger issue is the return loss. From 1MHz to 100MHz return loss should be at least -20 to 22dB. At 1.3GHz it should be greater than -10dB. It may help to improve the impedance continuity for the PCB/cable design to solve this issue. We can take a look at the layout if you would like assistance on reviewing. 

    Best Regards,

    Casey 

  • Hello Casey,

    Thanks for the information on return loss, we didn't look at this parameter enough and will seriously consider it on the next loop.

    Regarding the Eye diagram directly on the FPD Link, what is the exact register configuration ?

    I have the following:

    0x5B: FPD3_TX_MODE = 001

    0x5C : FORCE_LINK_RDY FORCE_LINK_RDY_P1 = 1

    0x20 = FREEZE_DES_CAP = 1

    But it looks like the back channel is still there on the scope

    Best regards,

    Alexandre

  • Sorry, i mean the forward channel since the deserializer is disconnected.

    Below the scope screen

  • Alexandre,

    Please disconnect the serializer from the deserializer and plug the output of the cable which would go into the deserializer directly into the scope. Then force link ready and the single FPD mode in order to make the serializer think there is a DES connected. Then you can look at the forward channel eye without any back channel.

    Best Regards,

    Casey 

  • Hello Casey,

    Thanks for the explanation.

    One last question regarding the quality of the FPD Link.

    Why do you need such return loss performance between 1 and 100MHz ? is it for the forward and back channel ?

    We have the SDD11 requirement by frequency, but not the S11, do you have them or is there a way to extrapolate ?

    Thanks,

    Best regards,

    Alexandre

  • Hello Casey,

    I just make a measurement directly on the Serializer output PCB board, and i have the following (CDR loop BW = 4.8 MHz)

    The results looks better, but i am far from the results shown page 132 of the 941 datasheet.

  • Hello Alex,

    Indeed the results look much better. The output jitter characteristic should be dictated by the system design. The two main factors which should influence this result would be the input jitter characteristics of the DSI input clock as well as the PCB trace design from the pin of our device out through the connector. Any impedance discontinuity in this path will cause the eye to close. 

    The results shown on page 132 are ideal results taken using a clean DSI generator source and an ideal board layout for verification purposes. 

    Best Regards,

    Casey