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Part Number: SN75DP130
We have a Cyclone 10 GX based custom board with SN75DP130 re-driver and a mDP connector. We are trying to port Altera's DP IP in TX-Only mode. Because of schematic issues, XCVR lanes form FPGA are connected in the reverse order i.e., lane_0 from FPGA is connected to IN3 on re-driver (polarity is not inverted). We are using DP breakout boards between FPGA board and Monitor to properly map lane order.
I am trying to bring up DP_TX in single lane mode. HPD is working fine, link training is happening properly on AUX channel. But the DP_TX IP is going into VIDEO_IDLE mode instead of NORMAL_VIDEO mode. If IN0-IN2 are not actively driven and only IN3 is driven, does SN75DP propagate it on OUT3?
You have to use I2C to disable link training and manually enable all lanes when connecting lane 0 to IN3 of DP130.
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In reply to David (ASIC) Liu:
Thanks for your time.
>> You have to use I2C to disable link training and manually enable all lanes when connecting lane 0 to IN3 of DP130.
Does it mean that only IN3 of SN75DP is getting enabled in my case?
If I configure DP_TX in 4-lane mode (but the order going to SN75DP will be in reverse. i.e, tx -> IN3 and tx -> IN0) and appropriately re-order the lane at the monitor/display end, will default link training work?
The datasheet has register descriptions but not any example programming sequences. Can you please let me know where I can find example sequences?
In reply to Bhargav Marpuri:
If DP130 link training is enabled and only one DP lane is enabled, DP130 will only enable DP0 and disable DP1, 2, and 3. If lane 0 is connected to DP3, you have to disable the link training and manually enable DP3.
4 lane would still work as long as the lane order is the same on the input and the output of the DP130.
For SW example, please use this app note as a starting point: http://www.ti.com/lit/an/slla349/slla349.pdf.
I am still using 1-lane DP_TX and connected it to IN0 of SN75DP130. Link training is enabled. When I look at DP130 register values before and after link training, they look fine. But still monitor goes into sleep (power saving) mode. Can you please let me know if the register values are fine?
Some DP130 registers (0x01 to 0x17) have default values.
Does DP 4-lane mode works? If DP 4 lane mode works, would you please dump out both the DPCD and I2C registers?
Could you please check HPD_SNK and HPD_SRC? Are they staying high or low?
What is the condition for the FPGA to go into the VIDEO_IDLE mode?
Thanks for all the support.
The behavior is same with 4-lane mode too. HPD coming to FPGA is high, Link Training is successful and monitor going to idle state.
HPD_SNK and HPD_SRC are high throughout the experiment.
I have raised a query on Altera Forum to understand what drives DP_Source IP into VIDEO_IDLE mode.
When we started probing the DP_TX IP core status deeper, we found that the main link is not up consistently. Whenever the link goes down, the IP is going into VIDEO_IDLE mode. When the link goes up, IP transits from VIDOE_IDLE mode to NORMAL_VIDEO mode, but it does not stay there for long to view the video on monitor. Are there similar registers in SN75DP130 that denote the main link status?
DP130 does not report main link status.
Can the FPGA read the DPCD register 0x00202h, 0x00203h, 0x00204h, and 0x00205h? These are the registers sink uses to report the status of the link training.
Can you also disable DP130 squelch (register 0x03h) to see if the link is able to stay up?
Sorry for the delayed response. DPCD registers 0x00202 - 0x00205 are always 0. Disabling squelch did not have any effect.
If the sink DPCD register 0x00202 - 0x00205 reads back as 0, then the link training is not successful.
Do you have a DPA-400 or an AUX snoop tool that can look at the AUX traffic?
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