This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • Resolved

TIOS101: TIOS101 Power Up Sequence

Prodigy 10 points

Replies: 1

Views: 43

Part Number: TIOS101

I am using the TIOS101 (no internal LDO) in a circuit where the VCC_IN can be un-powered and VCC pin can be powered or vice versa.

I noticed that when VCC_IN is un-powered and the VCC pin is powered (24V), the VCC_IN pin continually switches on/off. It back feeds current into my un-powered 5V circuit lifting the voltage to about 3V (even with a 500 Ohm resistor connected across from VCC_IN to GND). It seems like the TIOS101 exits the UVLO state and then the voltage on VCC_IN starts ramping down to 1.5V and then it repeats.

The TDS states that: "VCC_IN and VCC domains can be powered up in any sequence. In the event of VCC is powered and VCC_IN is
not, the OUT pin remains in high impedance."

The output seems to be in high Z under this condition because the enable pin is low, but why is the VCC_IN pin back feeding current into my circuit?


  • Hi Bart,

    The TIOS101 datasheet does state that the VCC_IN and VCC domains can be powered up in any sequence.  This is correct and the TIOS101 will not suffer any damage or consequence of having only one of the supply rails powered while the other rail is off.  However, that being said, you have found an odd behavior that probably deserves an added description in a future version of the datasheet.  The TIOS101 was intended to operate with both supply rails active instead of only one. This behavior you are seeing is only present when VCC is active and VCC_IN is not active.  Once both rails are properly supplied, the TIOS101 will operate as intended.

    As you know there are three versions of the TIOS101 where two of them output the internal LDO voltage, and the other version uses an externally supplied voltage on the VCC_IN pin.  The core design of all these three devices is basically the same except in the use of the LDO and how some internal signals are referenced through pullup resistors, etc.  The issue comes in how the device determines what version it is and whether to enable the internal LDO or use an external voltage on the VCC_IN pin.

    The TIOS101 (non-LDO) version of the device has an internal connection between the VCC_IN pin and a version selection node.  If the device detects a voltage on this node, then it will disable the LDO and use the external voltage on the VCC_IN pin.

    The TIOS101-3 and TIOS101-5 versions do not have this connection to the version selection node since the VCC_IN is now an output of the internal LDO voltage.  Therefore, the digital core will see this version node as floating and enable the LDO.

    When the TIOS101 VCC_IN is left un-powered while VCC is powered, that the device will NOT detect a voltage on the internal version node and enable the LDO just as if this was a TIOS101-3/5 device.  As the LDO powers up, the enable signal will go low and cause the LDO enable to oscillate until the VCC_IN voltage is applied.  Since the TIOS101 version is not intended to use the internal LDO, the internal power is being supplied through these various pullup resistors and the frequency of oscillation will be dependent on the load capacitance on the VCC_IN pin.  Varying the capacitance will change the RC constant.  If you add more capacitance to the VCC_IN pin, it will take longer to charge and therefore the internal voltage thresholds will take longer to cross causing a slower oscillation.  Observing this pin with an oscilloscope will display a waveform that resembles a sawtooth.

    The TIOS101 was not intended to be functional or used in applications where only one supply is active at a time and therefore it assumes that both supplies will be supplied and active within a short period of time.  The exact timing of how these are supplied is not critical because once a voltage is supplied to the VCC_IN pin, the internal LDO will be disabled.

    The voltage threshold output on the VCC_IN pin in this scenario should not exceed 3.46V before it disabled because this is the maximum 3.3V LDO output voltage.  However once it is disabled the voltage will drop until is is approximately 1.1V which is the lower threshold and the LDO will once again be enabled.  Unfortunately this cannot be disabled in the current version of the device.  Adding capacitance will slow this oscillation down until the VCC_IN can be supplied, otherwise you could always use the LDO version of the device to make sure this rail is always powered when VCC is powered.  This could be used independently of the 5V rail you are using for the rest of your board.

    I hope this explains the situation you are seeing.



This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.