DS100DF410: wrong packeges at low temp,

user6288916

Part Number: DS100DF410

Dear Sir,

We are using DS100DF410 for SFP+ for 10G rate ports. We are having issues with environment temperature changes when the component is at the 10.3125G data rate. The product must meet ambient temperature from -40 to 60 °C. Under normal temperature and high temperature, DS100DF410 can send and receive packets normally. But when the temperature drops to -40 °C, wrong packets will appear. By reading the values of registers 0x27 and 0x28, when environment temperature changes and gets close to -40 °C, the VEO and/or HEO of the DS100DF410 became worse.

reg info:

0xff 0xf

0x31 0x60

0x1e 0xe1

0x15 0x73

0x13 0x34

0x2f 0xf4

0x36 0x71

0x60 0x0

0x61 0xb2

0x62 0x90

0x63 0xb3

0x3a 0x0

0x64 0xff

0x2d 0x82

                 0x27        0x28
25 °C        0x24        0x44
-40 °C        0x20        0x2a

then in -40°C we try to modify some reg info, the VEO and/or HEO of the DS100DF410 became better(0x27=0x2a,0x28=0x62),but wrong packets still exist

reg info(we change reg of the retimer which is the sink of the switch, all channels are the same config):

0x31 0x00

0x2d 0x88

0x03 0x00

0x3a 0x00

Our topology is in the annextopo.docx

What's your opinion

over 4 years ago

0 Rodrigo Natal over 4 years ago

TI__Mastermind 19135 points

Hi,

Have you tried implementing retimer Rx adapt mode 2 (0x31 = 0x40, DFE enabled)? I believe that mode should yield a better result. I would also recommend to set disable EQ_LIMIT_EN (limiting CTLE output mode) by setting 0x13[2]=0 if using the retimer DFE.

Please try the settings above and record the values observed at three temperature corners (cold, room , and hot) for the following retimer registers:

0x03, 0x27, 0x28, 0x71, 0x72, 0x73, 0x74, 0x75
Note: For this test the CTLE should be allowed to adapt (i.e. set 0x2D[3] = 0)

Cordially,

Regards,

Rodrigo Natal

0 user6288916 over 4 years ago in reply to Rodrigo Natal

Prodigy 30 points

Hi,Rodrigo

I have tried your suggestion in cold temp ,in this situation,wrong packegs are still exists and channel 1 became worse

the retimer which is the sink of the switch registers record:

reg	Channel 0	Channel 1	Channel 2	Channel 3
0x03	0x00	0x00	0x00	0x00
0x27	0x23	0x0c	0x2a	0x24
0x28	0x38	0x0f	0x32	0x3a
0x71	0x20	0x20	0x0a	0x20
0x72	0x00	0x00	0x01	0x00
0x73	0x02	0x09	0x13	0x06
0x74	0x00	0x10	0x03	0x18
0x75	0x04	0x10	0x10	0x03

the retimer which is the source of the switch registers record:

reg	Channel 0	Channel 1	Channel 2	Channel 3
0x03	0x00	0x02	0x08	0x04
0x27	0x26	0x32	0x33	0x2c
0x28	0x42	0x63	0x6c	0x63
0x71	0x25	0x26	0x25	0x24
0x72	0x14	0x14	0x12	0x10
0x73	0x16	0x11	0x10	0x10
0x74	0x01	0x10	0x14	0x16
0x75	0x13	0x01	0x10	0x10

room and hot temp are testing now , Please help to see the low temperature first,thank you!

0 user6288916 over 4 years ago in reply to user6288916

Prodigy 30 points

Hi,Rodrigo

in room temp,wrong packegs are still exists

the retimer which is the sink of the switch registers record:

reg	Channel 0	Channel 1	Channel 2	Channel 3
0x03	0x00	0x00	0x00	0x00
0x27	0x26	0x22	0x2c	0x26
0x28	0x4e	0x32	0x44	0x42
0x71	0x20	0x20	0x0a	0x20
0x72	0x00	0x00	0x01	0x00
0x73	0x02	0x05	0x13	0x06
0x74	0x00	0x00	0x03	0x18
0x75	0x04	0x07	0x10	0x03

the retimer which is the source of the switch registers record:

reg	Channel 0	Channel 1	Channel 2	Channel 3
0x03	0x01	0x50	0x08	0x04
0x27	0x2b	0x35	0x35	0x31
0x28	0x3f	0x72	0x66	0x60
0x71	0x25	0x21	0x25	0x24
0x72	0x14	0x12	0x12	0x10
0x73	0x16	0x02	0x10	0x10
0x74	0x01	0x14	0x14	0x16
0x75	0x13	0x10	0x10	0x10

in hot temp,no wrong packegs appeared

the retimer which is the sink of the switch registers record:

reg	Channel 0	Channel 1	Channel 2	Channel 3
0x03	0x00	0x00	0x00	0x00
0x27	0x26	0x23	0x2c	0x25
0x28	0x52	0x40	0x46	0x42
0x71	0x20	0x20	0x0a	0x20
0x72	0x00	0x00	0x01	0x00
0x73	0x02	0x05	0x13	0x06
0x74	0x00	0x00	0x03	0x18
0x75	0x04	0x07	0x10	0x03

the retimer which is the source of the switch registers record:

reg	Channel 0	Channel 1	Channel 2	Channel 3
0x03	0x01	0x50	0x08	0x04
0x27	0x29	0x36	0x34	0x31
0x28	0x3f	0x6c	0x63	0x5d
0x71	0x25	0x21	0x25	0x24
0x72	0x14	0x12	0x12	0x10
0x73	0x16	0x02	0x10	0x10
0x74	0x01	0x14	0x14	0x16
0x75	0x13	0x10	0x10	0x10

0 Rodrigo Natal over 4 years ago in reply to user6288916

TI__Mastermind 19135 points

Hi,

Do you only see bit errors on retimer sink channel 1, or do you see them on all four retimer channels?
The retimer eye opening values are certainly much worse for channel 1. Is there anything different about your system board traces for those channels? For example are channel 1 trace lengths the shortest or longest on your board?
At this point I speculate that the issue is related to over-equalization. Suggestions below:

Disable post-cursor de-emphasis on transmitter signals to retimer Rx inputs. Zero post-cursor de-emphasis should be applied
Try the retimer Rx setting optimization routine below, which TI recommends for cases where there is over-equalization issue

Suggested operations for over‐EQ scenario

Step 1: Force CTLE = 0x00, set retimer to adapt mode 0 (no adaption)

REG	Value	Comment
0x31	0x00	Set Adapt mode 0
0x2D	0x88	Enable EQ override
0x03	0x00	Set EQ = 00
0x3A	0x00	Set EQ = 00
0x0A	0x1C	Puts the CDR into RESET
0x0A	0x10	Releases the CDR from reset

Step 2: Enable DFE and set tap 1 to positive polarity

REG	Value	Comment
0x1E	0xE1	Enable DFE
0x12[7]	0	Set DFE tap 1 polarity to 0

Step 3: Incrementally step through tap 1 weight values, to see which one yields the best retimer eye opening

Loop for optimizing the DFE attenuation setting

REG Value Comment

0x12[4:0] 0x02‐0x1A Set DFE tap 1 to desired weight

0x0A 0x1C Puts the CDR into RESET

0x0A 0x10 Releases the CDR from reset

0x02[4] Read CDR lock status

0x27 Read HEO

0x28 Read VEO

Note: It is recommended to allow for ~20ms wait time after implementing a CDR reset and release operation

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DS100DF410: wrong packeges at low temp,