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Part Number: SN65MLVD202A
I have an application in which I am using this IC to convert LVDS differential signals to single-ended signals and then use it with FPGA.
I have been provided with the above reference circuit and I am not able to understand the termination network here. Please find below points.
For the receiver section, it's easy to understand that the aux line has 100ohm differential impedance and its terminated by Split termination technique with the help of R6, R7, R8, R9,
that combination of resistor makes it 2 x (34.8 ohm + 15.4 ohm) = 100.4ohm which is near to 100ohm and that's ok.
(1)For the Driver section why its terminated with help of R3, R4 first(which seems like source termination) and then split terminated with help of R7 and R8?
here its 2 x 15.4 ohm = 30.8 ohm. I especially don't understand this part of the termination.
(3)Can this IC directly support 100ohm differential lines?
(4)Can we simplify this complex termination network?
Where is that reference circuit from? We have an EVM for this device with a schematic you can reference on the last page of this user's guide: http://www.ti.com/lit/ug/sllu039b/sllu039b.pdf
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In reply to I.K. Anyiam:
i got that circuit from client and answer which is given is not solving my question.
Reference of EVM is not sufficient to answer my question
In reply to Abhi Choksi:
1. The load resistance for the device can be as low as 30 ohms so there's no issue with this termination, but you would have to ask your client why they chose to terminate it this way
3. Yes, it is meant for 100 ohm differential transmission media
4. Yes, as shown by the schematic in the EVM guide I sent
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