This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLK10232: 10GBASE-KR auto-negotiation and link training

Part Number: TLK10232

Hi,

We have incorporated the TLK10232 into our current design which involves connecting a camera sensor on the low speed side and the high speed side is connected to an Intel Arria10 FPGA 10GBASE-KR PHY. The Intel FPGA Arria10 10GBASE-KR PHY core supports auto-negotiation, link training, and FEC. Upon bringing the TLK10232 out of reset and power-down, we follow the TLK10232 bring-up procedure "KR with Auto Negotiation, Link Training, FEC, with 156.25 MHz / 312.5 MHz Refclk". We are using a 156.25Mhz Refclk. When performing the bring-up procedure, we first get stuck polling the HS_AGC_LOCKED bit as this never gets set. 

Some other questions are:

1) The datasheet says that the HS PLL Multiplier needs to be 16.5x however the default is 20x. The bring-up procedure doesn't mention changing this?

2) Another test we performed was that we were able to disable / enable link training on the FPGA side and the TLK10232 reflected the correct value in the AN_LP_ABILITY of the AN_STATUS register. So there seems to be some sort of communication going on. However, when we did this in the reverse order the FPGA did not detect AN_LP_ABILITY at all.

Do you have any suggestions to debug why we can't obtain the HS_AGC_LOCKED or succeed past the auto negotiation and link training?

  • Hi,

    1) The datasheet says that the HS PLL Multiplier needs to be 16.5x however the default is 20x. The bring-up procedure doesn't mention changing this?

    Correct, as per the datasheet the high-speed PLL multiplier needs to be 16.5x for 10.3125Gbps operation with 156.25MHz REF_CLK.

    Table 3-1. Specific Line Rate and Reference Clock Selection for the 10GBASE-KR Mode:

    LOW SPEED SIDE

    HIGH SPEED SIDE

    Line Rate

    (Mbps)

    SERDES PLL Multiplier

    Rate

    REFCLKP/N (MHz)

    Line Rate

    (Mbps)

    SERDES PLL Multiplier

    Rate

    REFCLKP/N (MHz)

    3125

    10

    Full

    156.25

    10312.5

    16.5

    Full

    156.25

    3125

    5

    Full

    312.5

    10312.5

    8.25

    Full

    312.5

    2) Another test we performed was that we were able to disable / enable link training on the FPGA side and the TLK10232 reflected the correct value in the AN_LP_ABILITY of the AN_STATUS register. So there seems to be some sort of communication going on. However, when we did this in the reverse order the FPGA did not detect AN_LP_ABILITY at all. Do you have any suggestions to debug why we can't obtain the HS_AGC_LOCKED or succeed past the auto  negotiation and link training

     

    Some items for you to check:

    • Can you confirm that you are configuring MODE_SEL pin and Register 1E.0001 bit 10 for KR operation? If using Clause 45 mode SW_PCS_SEL (Register 1E.0001 bit 11) should be set to 1 for KR.

    Table 2-3. TLK10232 Operating Mode Selection

    ST = 0 (Clause 45)

    ST = 1 (Clause 22)

    {MODE_SEL pin, Register

    1E.0001 bit 10}

    1x

    10G

    10G

    01

    10G

    10G

    00

    10G-KR/1G-KX (Determined by Auto Neg)

    1G-KX

    (No Auto Neg)

    • Can you confirm link training enabled on the TLK PHY device? See pertinent register bit below.

    Table 8-68. LT_TRAIN_CONTROL

    Device Address: 0x01 Register Address: 0x0096 Default: 0x0002

    Bit(s)

    Name

    Description

    Access

    15:2

    RESERVED

    For TI use only. Always reads 0.

    RW

    1

    LT_TRAINING_ENABLE (RXG)

    1 = Enable start-up protocol as per 10GBASE-KR standard(Default 1’b1)

    0 = Disable start-up protocol

    This bit should be set to HIGH for autotrain mode to function correctly

    RW

    0

    LT_RESTART_TRAINING (RXG)

    1 = Reset link/auto train

    0 = Normal operation (Default 1’b0)

    RW/SC

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • Rodrigo,

    ST = 0 and MODE_SEL = 0. SW_PCS_SEL also is set to 1. LT_TRAIN_CONTROL is also set to the default 0x02 with LT_TRAINING_ENABLE enabled.

    Do you have any suggestions to debug why we can't obtain the HS_AGC_LOCKED or succeed past the auto  negotiation and link training. The bring up procedure says this should become locked. 

    - Mike

  • Hi,

    I don't yet have an explanation for why HS_AGC_LOCKED is not asserting. If you set HS_AGCCTRL[1:0]=b10 to force the attenuator off are you able to bring up the KR link?

    -Rodrigo

  • Rodrigo,

    If I force the attenuator off I do not make any more progress. I also do not see any fault bits set either indicating that the auto negotiation failed or the link training failed. Would this indicate that the part never tried to auto negotiate or link train? Is there any registers we can look at in particular that would indicate our issue is with the setup of the TLK10232 or the FPGA?

    - Mike

  • Hi Mike,

    • You may try checking to see if you are able tor trigger training restart via bit below.

    Table 8-68. LT_TRAIN_CONTROL

    Device Address: 0x01 Register Address: 0x0096 Default: 0x0002

    Bit(s)

    Name

    Description

    Access

    15:2

    RESERVED

    For TI use only. Always reads 0.

    RW

    1

    LT_TRAINING_ENABLE (RXG)

    1 = Enable start-up protocol as per 10GBASE-KR standard(Default 1’b1)

    0 = Disable start-up protocol

    This bit should be set to HIGH for autotrain mode to function correctly

    RW

    0

    LT_RESTART_TRAINING (RXG)

    1 = Reset link/auto train

    0 = Normal operation (Default 1’b0)

    RW/SC

    • See TLK10232 datasheet tables 8-69 through 8-73, describing the various link_training status and control registers. The high-level LT status is captured on the register shown below.

    www.ti.com/.../tlk10232.pdf

    Table 8-69. LT_TRAIN_STATUS

    Device Address: 0x01 Register Address: 0x0097 Default: 0x0000

    Bit(s)

    Name

    Description

    Access

    3

    LT_TRAINING_FAIL (RXG)

    1 = Training failure has been detected

    0 = Training failure has not been detected

    RO

    2

    LT_START_PROTOCOL (RXG)

    1 = Start up protocol in progress

    0 = Start up protocol complete

    RO

    1

    LT_FRAME_LOCK (RXG)

    1 = Training frame delineation detected

    0 = Training frame delineation not detected

    RO

    0

    LT_RX_STATUS (RXG)

    1 = Receiver trained and ready to receive data

    0 = Receiver training in progress

    RO

    Regards,

    Rodrigo Natal

    HSSC Applications Engineer

  • Rodrigo, 

    Triggering the restart link training also does not get me any further.

    I tried to take a step back and disable auto negotiation and link training. I see the PCS_FAULT bit set. What causes this fault bit to be set? I was unable to get PCS_LOOPBACK to work either. 

    Is there any simple steps I can perform for a sanity check that the HW is working as expected?

    - Mike

  • Hi,

    If you disable KR link training on your FPGA Tx and simply output 10.3125Gbps PRBS data, is the TLK device able to lock to this high-speed data and run its PRBS checker without any error? Refer to TLK datasheet for PRBS test mode configuration instructions.

    Cordially,

    Rodrigo Natal

  • Rodrigo,

    I'm in the process of trying your previous suggestion. We are using Intel's example project for the 10GBASE-KR phy and are still struggling to get the AN and LT to work. Using this example project, I now get the RX_FIFO_OVERFLOW bit set in CHANNEL_STATUS_1. What causes this overflow?

    Also, if I disable the sequencer in the FPGA core and transmit a PRBS31 bit pattern I then see the HS_AGC_LOCKED bit go high (which I previously have never got to lock before).

    If trying AN and LT the REMOTE_FAULT bit in the AN_STATUS is set and LT_START_PROTOCOL is set in LT_TRAIN_STATUS. 

    Do you have any further recommendations based on the information above?

    - Mike

    • Related to: Using this example project, I now get the RX_FIFO_OVERFLOW bit set in CHANNEL_STATUS_1. What causes this overflow
      • In 10GKR and 10G modes, high indicates overflow has occurred in the receive datapath (CTC, or Clock Tolerance Compensation) FIFO.
      • Question: Have you tried reducing the packet size, or reducing the utilization rate (i.e. more idles transmitted)?
      • Question: With regard to your REFCLK for 10G KR, are you using a low-jitter clock? per the datasheet: A low-jitter reference clock should be used, and its frequency accuracy should be within ±200 PPM of the incoming serial data rate (±100 PPM of nominal data rate).

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • Rodrigo,

    Disregard my previous post, I believe I left the PRSBEN pin floating in the FPGA example design which caused this issue. After resolving that, I can now see an attempt for AN and LT on the link. I actually see the LT_RX_STATUS bit go high. I never see the AN_COMPLETE bit set though. The issue is, as far as I can tell, the FPGA and TLK10232 attempt to AN and LT and then a fault occurs and then the process starts over. This happens indefinitely if I disable the AN timeout in the FPGA. 

    So where I am right now, it appears that the two parts are communicating but are having data integrity issues across the link. I tried maxing the HS_SWING value but no success. Do you have any other suggestions for optimizing a "high frequency, long transmission line"? I am trying to read through the 10GBASE-KR Link Optimization Guide.

    I also can't adjust the gains in the FPGA because when I try to put the TLK10232 into test pattern mode the FPGA doesn't seem to be seeing anything. As far as I can tell from the datasheet and bring-up procedure, I should just have to set PCS_TP_CONTROL=0x10 to enable PRBS31 on the output. Is this correct? If so, I can't get the FPGA to lock to any PRBS31 data on it's receiver. 

    - Mike

    • If additional optimization is needed for the link case of TLK Tx to FPGA Rx, the TLK has output post-cursor and pre-cursor de-emphasis available. I would suggest to tune these Tx EQ parameters. See parameters TWPOST1, TXPRE and TWPOST2 per the datasheet table included below. Out of these parameters I would expect TWPOST1 to help the most. 

    Table 8-9. HS_SERDES_CONTROL_4

     

    Device Address: 0x1E                               Register Address:0x0005                                                                 Default:0x2000

    Bit(s)

    Name

    Description

    Access

    15

    HS_RX_INVPAIR (RXG)

    Receiver polarity.

    0 = Normal polarity. HSRXxP considered positive data. HSRXxN considered negative data

    (Default 1’b0)

    1 = Inverted polarity. HSRXxP considered negative data. HSRXxN considered positive data

    RW

    14

    HS_TX_INVPAIR (RXG)

    Transmitter polarity.

    0 = Normal polarity. HSTXxP considered positive data and HSTXxN considered negative data (Default 1’b0)

    1 = Inverted polarity. HSTXxP considered negative data and HSTXxN considered positive data

    RW

    13

    RESERVED

    For TI use only (Default 1’b1)

    RW

    12:8

    HS_TWPOST1[4:0] (RXG)

    Adjacent post cursor1 Tap weight. Selects TAP settings for TX waveform. (Default 5’b00000 ) Refer Table 8-10.

    RW

    7:4

    HS_TWPRE[3:0] (RXG)

    Precursor Tap weight. Selects TAP settings for TX waveform. (Default 4’b0000) Refer Table 8-12.

    RW

    3:0

    HS_TWPOST2[3:0] (RXG)

    Adjacent post cursor2 Tap weight. Selects TAP settings for TX waveform. (Default 4’b0000) Refer Table 8-11.

    RW

    • For FPGA Tx to TLK Rx link case the TLK has auto adaptive Rx EQ (DFE + FFE) which does not require end user configuration. Beyond that, HS_EQPRE[2:0] parameter (see table below) may be tuned to adjust the Serdes Rx precursor equalizer setting

    Device Address: 0x1E Register Address:0x0004 Default:0x1500

    Bit(s)

    Name

    Description

    Access

    15

    HS_ENTRACK (RXG)

    HSRX ADC Track mode.

    0 = Normal operation (Default 1’b0)

    1 = Forces ADC into track mode

    RW

    14:12

    HS_EQPRE[2:0] (RXG)

    Serdes Rx precursor equalizer selection

    000 = 1/9 cursor amplitude

    001 = 3/9 cursor amplitude (Default 3’b001)

    010 = 5/9 cursor amplitude

    011 = 7/9 cursor amplitude

    100 = 9/9 cursor amplitude

    101 =11/9 cursor amplitude

    110 = 13/9 cursor amplitude

    111 = Disable

    RW

    • Beyond setting PRBSEN=1, the only other configuration you should need to do for PRBS is setting HS_TEST_PATT_SEL[2:0]=b111 for PRBS31. refer to datasheet table 8-22.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer