Hi,
We have incorporated the TLK10232 into our current design which involves connecting a camera sensor on the low speed side and the high speed side is connected to an Intel Arria10 FPGA 10GBASE-KR PHY. The Intel FPGA Arria10 10GBASE-KR PHY core supports auto-negotiation, link training, and FEC. Upon bringing the TLK10232 out of reset and power-down, we follow the TLK10232 bring-up procedure "KR with Auto Negotiation, Link Training, FEC, with 156.25 MHz / 312.5 MHz Refclk". We are using a 156.25Mhz Refclk. When performing the bring-up procedure, we first get stuck polling the HS_AGC_LOCKED bit as this never gets set.
Some other questions are:
1) The datasheet says that the HS PLL Multiplier needs to be 16.5x however the default is 20x. The bring-up procedure doesn't mention changing this?
2) Another test we performed was that we were able to disable / enable link training on the FPGA side and the TLK10232 reflected the correct value in the AN_LP_ABILITY of the AN_STATUS register. So there seems to be some sort of communication going on. However, when we did this in the reverse order the FPGA did not detect AN_LP_ABILITY at all.
Do you have any suggestions to debug why we can't obtain the HS_AGC_LOCKED or succeed past the auto negotiation and link training?