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TL16C752D: Receive Interrupt clear way when Receive FIFO becomes empty (2)

Part Number: TL16C752D

Hi Team,

 *This is a continuation of the thread, TL16C752D: Receive Interrupt clear way when Receive FIFO becomes empty.

My customer have found a case where the reception interrupt of TL16C752DPFBRQ1 cannot be cleared and a phenomenon that seems to be the cause.
The address bus is released at the end of the read cycle from the CPU to the TL16C752D, but spike-like noise occurs at the time of release and the address signal connected to the TL16C752D changes.
They believe that this may be because the requirement for "Address hold time" min 7ns "of TL16C752D is not satisfied.
(Address hold time is min 0ns for TL16C752B)

Is it not possible to confirm the phenomenon that "Interrupt output is not cleared if the address hold time does not satisfy the required specification" min 7ns "" when reading the RHR due to a reception interrupt on the TL16C752D, by using simulations?
Than you.

Best Regards,

Koshi Ninomiya