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DS110DF111: SGMII signal sometimes can not be locked by default
Part Number: DS110DF111
I would like to ask, what ist the difference between DS110DF111 Channel Register 0x03 and Channel Register 0x3A, since both of them have the name "CTLE".
I use DS110DF111 for SGMII, since sometimes there are connection problem of SGMII interface, I would like to know, if both TX and RX are locked (Channel A and Channel B), does it mean the Retimer is like transparent and is not guilty for the SGMII connection problem?
The Channel Register 0x02 have Bit4 for Lock and Bit5 for CDR Lock, whats the difference? If I read 011 from Bit5 to Bit3, does it mean, the signal is locked?
1). In normal adaptive mode, device automatically finds best CTLE settings for VCO divide by 1 and divide by 2. This CTLE setting is saved in reg 0x03 and 0x52(please note data sheet for details). For divide by 4 or 8 Reg 0x3A is used for CTLE setting. For example, if VCO is running at 10G, then if the incoming data rate is 2.5G or 1.25G(VCO divide by 4 or divide by 8 respectively) then device automatically uses reg 0x3A content for the CTLE setting. On the other hand if the data rate is 10G or 5G then device automatically finds best CTLE settings and this setting is saved in reg 0x03 and 0x52.
2). When both TX and RX are locked it means the retimer are transparent. CTLE block is before CDR block and if the CTLE setting is not optimum both parts could be locked but there may be bit error - due to the CTLE settings. To check if CTLE settings is optimum, you can check HEO and VEO values. We should optimize CTLE setting so we can have more than 0.4UI HEO and at least 200mV for VEO. Please note data sheet for HEO and VEO details.
3). When bits 4 and 3 of reg 0x02 status register are set this means device is locked. During lock process, bit 3 may turn off or on but when lock is achieved both bits 4&3 are set. Again, when both bits 4&3 are set this means device is locked and we should make sure this condition is met.
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In reply to Nasser Mohammadi:
thank you for the quick reply!
Ein further question:
how can I reset the retimer? I have problem, most of time the retimer can lock the signal, sometimes don't, and in this case, I want to do a reset on the retimer (is it called self-clearing?), how can I reset the retimer by software?
In reply to Lin Lu:
Please note register 0x0A[3:2] in the data sheet. Setting these bits, reset the channel and these are not self clearing.
The retimer works well with long distance signal (the signal is always locked by default without setting the equalizer), but I have very often problems with very short distance signal (about 30mm plus connector). I tried to deaktive Adaption with following way:
Set Adapt mode 0
Enable EQ override
Set EQ = 00
Puts the CDR into RESET
Releases the CDR from reset
But it doesn't seems to help. HEO and VEO are very often 0.
Is there any way to solve my problem? I don't have much experience of setting equalizer (CTLE, DFE etc.).
Normally, if HEO and VEO are 0 this means CDR is not locked. When HEO/VEO is zero, you can read reg 0x02 multiple times to confirm device is not locked or it is going in and out of lock.
Given using long trace is fine and you are seeing this issue with short trace, perhaps there is some over-equalization. On your FPGA or signal source driving input of the DS110DF111, can you reduce amplitude and turn off any de-emphasis? Does this take care of the problem?
yes, the signal is not locked by checking register 0x02. But I can measure that, the output LOS/INT# (Pin13) is driven low, which means a valid signal is present on Channel A (in my case the channel with problem). What is the definition of a valid signal? Is it possible that the signal is valid but not locked?
ps: Pin 13 is LOS, not INT (Bit5 = 0)
Based on your observation, it seems there is signal but device is not able to lock to this signal. Please note as long as signal is typically 20mVp-p signal detect becomes active. A valid signal has 20mVp-p level - this is a definition of a valid signal.
Given your earlier comment that there is no problem with long trace and you see this issue with short trace only and your latest observation, i think there seems to be some level of over-equalization that is causing device to not lock.
In earlier post, we suggested to reduce signal source amplitude or de-emphasis. Please look into this and let us know.
the source signal is SGMII and I can not change the source amplitude, I noticed I can adjust de-emphasis in the retimer from 0dB to -12dB. Should I set the de-emphasis to 0dB or set it to -12dB?
sorry, I think I just asked a stupid question ,since the de-emphasis setting in retimer for output ist, not for input, I think it won't help me to adjust the de-emphasis in retimer.
I can not adjust the signal source. I have noticed that, I read from Register 0x24 the value 0x40 back, which means DFE Error - No Lock. I have already set the retimer to adaption mode 0 (no adaption). But it seems the signal can still not be locked.
I use the following routine to set the retimer to adaption mode 0:
set 0xFF to 0x04set 0x31 to 0x00set 0x2D to 0x88set 0x03 to 0x00set 0x3A to 0x00set 0x0A to 0x1Cset 0x0A t0 0x10
Am I doing it right? If I can not modified the source signal and adaption mode 0 doesn't help, are there any other possibilitys to fix the problem? Just keep in mind, the problem doesn't always happens, about 50% cases the signal is nicely locked without any issue.
I don't think changing de-emphasis on retimer is going to help. Of course you can try this.
Please send me email at email@example.com with your company email address so we can discuss this more closely. For now, i will close this thread and let's get more info through email.
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