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TIOS1013: Surge protection on TIOS101-3

Part Number: TIOS1013

hi,

We are doing functional as well as EMC testing for TIOS101-3 at the moment and hope that the performance of the TI chip meets requirements. 

We have one particular issue at hand regarding immunity to transient surge voltage. If we apply surge voltage (500V-12Ohm) to the OUT pin of the TIOS101-3, the chip undergoes reset. Attached is the screenshot for your reference. Looks like the output is off for a period of around 30ms and then it recovers again. We believe that the output reset happens because of Undervoltage detection by the chip.

Based on the datasheet, it looks like the device is safe for 1.2kv surge (500Ohm impedance). Is there any recommendation by TI regarding protection against transient surge? We don't want output reset/OFF till 1kV/12 Ohm surge.

Please advice.

Best Rgds,

kpk

  • Ki kpk,

    Yes, as specified in section 8.8.8 of the TIOS1013 datasheet, the device is capable of withstanding up to 1.2 kV of 1.2/50– 8/20μs IEC 61000-4-5surgewith a source impedance of 500Ω.  A 12Ω source impedance will pass significantly more current to the device pins during the pulse and an external TVS clamping diode will be required in the system to meet this more stringent requirement.

    I believe your assertion that the OUT re-enable after UVLO is the cause for the 30mS delay in the waveform.

    The TI Design TIDA-01478uses the SMAJ30CA diode to meet 1.2kV with a 40Ω source impedance.  I am not aware of a TI device that would meet the protection requirements of 12Ω and I am not aware of any testing I can point to that shows passing results with an impedance smaller than the 40Ω results in this TI Design.

    Are you asking for a recommendation on a specific diode part number that would meet this 12Ω source impedance requirement?  I currently do not have any specific recommendation available at this time and some work would need to be done to identify a suitable diode that has a max clamping voltage less than the TIOS1013's abs max rating, low enough leakage current and parasitic capacitance, and account for temperature de-rating etc. 

    Regards,

    Jonathan